2014 - IEEE Fellow For contributions to error-tolerant circuits and near-load voltage regulators
His main research concerns Electronic engineering, CMOS, Electronic circuit, Voltage and Soft error. His Electronic engineering research is multidisciplinary, incorporating elements of Buck converter, Process, Low-power electronics, Control theory and Decoupling. His CMOS study results in a more complete grasp of Electrical engineering.
The concepts of his Electronic circuit study are interwoven with issues in Microprocessor, Clock rate and Chip. His research in Voltage intersects with topics in Very-large-scale integration and Efficient energy use. His Soft error research is multidisciplinary, relying on both Capacitance and Transistor.
His scientific interests lie mostly in Electronic engineering, Electrical engineering, Voltage, Electronic circuit and CMOS. His Electronic engineering research is multidisciplinary, incorporating perspectives in Voltage droop, Microprocessor, Integrated circuit, Transistor and Signal. Tanay Karnik regularly links together related areas like Efficient energy use in his Voltage studies.
Many of his studies on Electronic circuit involve topics that are commonly interrelated, such as Clock rate. His work deals with themes such as Electrical impedance, Soft error, Converters and Buck converter, which intersect with CMOS. Tanay Karnik has included themes like Optoelectronics, Magnetic core, Transformer and Eddy current in his Inductor study.
The scientist’s investigation covers issues in Electrical engineering, Orbit, Spin-½, Efficient energy use and Cache. His Electrical engineering research incorporates themes from Energy harvesting and State. His research integrates issues of Optoelectronics and Orbit in his study of Spin-½.
His Efficient energy use research is multidisciplinary, incorporating elements of Enhanced Data Rates for GSM Evolution, Logic gate, Power management, MOSFET and CMOS. His Logic gate research focuses on Processor design and how it connects with Electronic engineering. His Electronic circuit study integrates concerns from other disciplines, such as Algorithm, Synchronous circuit and Beyond CMOS.
His primary scientific interests are in CMOS, Efficient energy use, Power management, Computer network and Spin-½. Tanay Karnik has researched CMOS in several fields, including Process, Electronic circuit, Logic family, Inverter and Circuit design. His biological study spans a wide range of topics, including Processor design, Electronic engineering and Control reconfiguration.
Tanay Karnik interconnects Interconnection and Logic gate in the investigation of issues within Efficient energy use. As a part of the same scientific study, Tanay Karnik usually deals with the Power management, concentrating on Enhanced Data Rates for GSM Evolution and frequently concerns with Embedded system. His research investigates the link between Spin-½ and topics such as Orbit that cross with problems in Optoelectronics, Voltage and Transistor sizing.
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Parameter variations and impact on circuits and microarchitecture
Shekhar Borkar;Tanay Karnik;Siva Narendra;Jim Tschanz.
design automation conference (2003)
Area-efficient linear regulator with ultra-fast load regulation
Peter Hazucha;Tanay Karnik;Bradley A. Bloechel;Colleen Parsons.
symposium on vlsi circuits (2005)
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee.
international solid-state circuits conference (2009)
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package
P. Hazucha;G. Schrom;Jaehong Hahn;B.A. Bloechel.
IEEE Journal of Solid-state Circuits (2005)
Review of On-Chip Inductor Structures With Magnetic Films
D.S. Gardner;G. Schrom;F. Paillet;B. Jamieson.
IEEE Transactions on Magnetics (2009)
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
K A Bowman;J W Tschanz;S L Lu;P A Aseron.
IEEE Journal of Solid-state Circuits (2011)
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging
J. Tschanz;Nam Sung Kim;S. Dighe;J. Howard.
international solid-state circuits conference (2007)
Design and reliability challenges in nanometer technologies
Shekhar Borkar;Tanay Karnik;Vivek De.
design automation conference (2004)
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process
P. Hazucha;T. Karnik;S. Walstra;B.A. Bloechel.
IEEE Journal of Solid-state Circuits (2004)
Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation
P. Hazucha;T. Karnik;J. Maiz;S. Walstra.
international electron devices meeting (2003)
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