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Electronics and Electrical Engineering

D-Index
51
Citations
11613
World Ranking
2628
National Ranking
1006

Research.com Recognitions

  • 2014 - IEEE Fellow For contributions to error-tolerant circuits and near-load voltage regulators

Overview

Tanay Karnik is affiliated with Intel in the United States. Their research spans primarily the fields of engineering and computer science, with a focus on electrical and electronic engineering as well as computer networks and communications.

Their recent publications cover various technical topics and include:

  • 2.5D and 3D Heterogeneous Integration: Emerging applications, 2021, IEEE Solid-State Circuits Magazine
  • Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems, 2022, 2022 23rd International Symposium on Quality Electronic Design (ISQED)
  • On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs, 2023, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Innovations for Intelligent Edge, 2022, ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
  • Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS)

The main research topics they have contributed to include:

  • 3D IC and TSV technologies
  • Interconnection Networks and Systems
  • Semiconductor materials and devices
  • Semiconductor Lasers and Optical Devices
  • Advancements in PLL and VCO Technologies
  • Telecommunications and Broadcasting Technologies
  • Advanced Wireless Communication Technologies

Tanay Karnik has published in frequent venues such as:

  • IEEE Solid-State Circuits Magazine
  • IEEE Journal of Solid-State Circuits
  • 2022 23rd International Symposium on Quality Electronic Design (ISQED)
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

Their work often involves collaboration with several frequent co-authors, including:

  • Anuradha Srinivasan
  • Srivatsa Srinivasa
  • Dileep Kurian
  • Vinayak Honkote
  • Satish Yada

Tanay Karnik was recognized as an IEEE Fellow in 2014 for contributions related to error-tolerant circuits and near-load voltage regulators.

Best Publications

  • Parameter variations and impact on circuits and microarchitecture

    Shekhar Borkar;Tanay Karnik;Siva Narendra;Jim Tschanz

  • Area-efficient linear regulator with ultra-fast load regulation

    Peter Hazucha;Tanay Karnik;Bradley A. Bloechel;Colleen Parsons

  • Characterization of soft errors caused by single event upsets in CMOS processes

    Unknown

  • Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

    Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee

  • A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

    P. Hazucha;G. Schrom;Jaehong Hahn;B.A. Bloechel

  • Review of On-Chip Inductor Structures With Magnetic Films

    D.S. Gardner;G. Schrom;F. Paillet;B. Jamieson

  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    K A Bowman;J W Tschanz;S L Lu;P A Aseron

  • Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

    J. Tschanz;Nam Sung Kim;S. Dighe;J. Howard

  • Design and reliability challenges in nanometer technologies

    Shekhar Borkar;Tanay Karnik;Vivek De

  • Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

    P. Hazucha;T. Karnik;S. Walstra;B.A. Bloechel

  • Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

    P. Hazucha;T. Karnik;J. Maiz;S. Walstra

  • Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/

    T. Karnik;B. Bloechel;K. Soumyanath;V. De

  • Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance

    James Tschanz;Keith Bowman;Steve Walstra;Marty Agostinelli

  • Circuit techniques for dynamic variation tolerance

    Keith Bowman;James Tschanz;Chris Wilkerson;Shih-Lien Lu

  • Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

    Arijit Raychowdhury;Dinesh Somasekhar;Tanay Karnik;Vivek De

  • Integrated on-chip inductors using magnetic material (invited)

    Donald S. Gardner;Gerhard Schrom;Peter Hazucha;Fabrice Paillet

  • Sub-90 nm technologies-challenges and opportunities for CAD

    Tanay Karnik;Shekhar Borkar;Vivek De

  • Integrated On-Chip Inductors with Magnetic Films

    D.S. Gardner;G. Schrom;P. Hazucha;F. Paillet

  • A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

    G. Schrom;P. Hazucha;J. Hahn;D.S. Gardner

  • Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

    Tanay Karnik;Yibin Ye;James Tschanz;Liqiong Wei

  • Integrated On-Chip Inductors With Magnetic Films

    D.S. Gardner;G. Schrom;P. Hazucha;F. Paillet

Frequent Co-Authors

Vivek De
Vivek De Intel (United States)
Donald S. Gardner
Donald S. Gardner Intel (United States)
James W. Tschanz
James W. Tschanz Intel (United States)
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
Shekhar Borkar
Shekhar Borkar Qualcomm (United States)
Keith Bowman
Keith Bowman Qualcomm (United States)
Shih-Lien Lu
Shih-Lien Lu Washington State University
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Siva G. Narendra
Siva G. Narendra Tyfone, Inc.
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology

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