2026 Puneet Gupta: Electronics and Electrical Engineering Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Electronics and Electrical Engineering	44	3697	3551	1341	1254	256	8831

Overview

Puneet Gupta is affiliated with the University of California, Los Angeles in the United States. Their research encompasses multiple areas within engineering and computer science, focusing particularly on electrical and electronic engineering as well as artificial intelligence.

The scientist has contributed to the fields of study including:

Engineering
Computer Science

Within these broad disciplines, they have worked extensively on subfields such as:

Electrical and Electronic Engineering
Artificial Intelligence
Hardware and Architecture
Computer Networks and Communications
Biomedical Engineering

Puneet Gupta's main topics of research interest include:

Neural Networks and Reservoir Computing
Photonic and Optical Devices
Optical Network Technologies
Advanced Memory and Neural Computing
Ferroelectric and Negative Capacitance Devices
Parallel Computing and Optimization Techniques
Stochastic Gradient Optimization Techniques

Their recent scholarly contributions consist of papers published across various venues, with notable works such as:

"Design Space Exploration for Chiplet-Assembly-Based Processors", 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"SUNRISE: Improving 3D mask Face Anti-spoofing for Short Videos using Pre-emptive Split and Merge", 2022, IEEE Transactions on Dependable and Secure Computing
"Massively parallel amplitude-only Fourier neural network", 2020, Optica
"High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator", 2022, Laser & Photonics Review
"Design and Testing of Integrated Photonic Chip for Convolution Neural Network", 2022, Imaging and Applied Optics Congress 2022 (3D, AOA, COSI, ISA, pcAOP)

The scientist frequently publishes in these venues:

arXiv (Cornell University)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Conference on Lasers and Electro-Optics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2022 IEEE Photonics Conference (IPC)

They collaborate often with several co-authors, including:

Shurui Li
Volker J. Sorger
Zibo Hu
Mario Miscuglio
Tianmu Li

Best Publications

Trading Accuracy for Power with an Underdesigned Multiplier Architecture

Parag Kulkarni;Puneet Gupta;Milos Ercegovac

659
Citations
Gate-length biasing for digital circuit optimization

Puneet Gupta;Andrew B. Kahng

265
Citations
Manufacturing-Aware Physical Design

Puneet Gupta;Andrew B. Kahng

262
Citations
Tool for modifying mask design layout

Andrew B. Kahng;Puneet Gupta;Dennis Sylvester;Jie Yang

260
Citations
Toward through-process layout quality metrics

Fook-Luen Heng;Jin-Fuw Lee;Puneet Gupta

250
Citations
Toward a methodology for manufacturability-driven design rule exploration

L. Capodlieci;P. Gulpta;A.B. Kahng;D. Sylvester

244
Citations
Reliable on-chip systems in the nano-era: lessons learnt and future trends

Jorg Henkel;Lars Bauer;Nikil Dutt;Puneet Gupta

240
Citations
Selective gate-length biasing for cost-effective runtime leakage control

Puneet Gupta;Andrew B. Kahng;Puneet Sharma;Dennis Sylvester

230
Citations
Method of IC fabrication, IC mask fabrication and program product therefor

Puneet Gupta;Fook-Luen Heng;Mark A. Lavin

228
Citations
Enhanced resist and etch CD control by design perturbation

Puneet Gupta;Andrew B. Kahng;Chul-Hong Park

218
Citations
Wafer topography- aware optical proximity correction for better DOF margin and CD control

Puneet Gupta;Andrew B. Kahng;Chul-Hong Park;Kambiz Samadi

189
Citations
Underdesigned and Opportunistic Computing in Presence of Hardware Variability

P. Gupta;Y. Agarwal;L. Dolecek;N. Dutt

186
Citations
Trading Accuracy for Power in a Multiplier Architecture

Parag Kulkarni;Puneet Gupta;Milos D. Ercegovac

167
Citations
Massively parallel amplitude-only Fourier neural network

Mario Miscuglio;Zibo Hu;Shurui Li;Jonathan K. George

163
Citations
A practical transistor-level dual threshold voltage assignment methodology

P. Gupta;A.B. Kahng;P. Sharma

162
Citations
Method and system for detailed placement of layout objects in a standard-cell layout design

Puneet Gupta;Andrew Kahng;Chul-Hong Park

158
Citations
Joining the design and mask flows for better and cheaper masks

Puneet Gupta;Andrew B. Kahng;Chul-Hong Park;P. Sharma

149
Citations
Detailed placement for improved depth of focus and CD control

P. Gupta;A.B. Kahngt;Chul-Hong Park

143
Citations
Gate-length biasing for runtime-leakage control

P. Gupta;A.B. Kahng;P. Sharma;D. Sylvester

137
Citations
Design sensitivities to variability: extrapolations and assessments in nanometer VLSI

Y. Cao;P. Gupta;A.B. Kahng;D. Sylvester

136
Citations

Frequent Co-Authors

Andrew B. Kahng University of California, San Diego

Dennis Sylvester University of Michigan–Ann Arbor

Nikil Dutt University of California, Irvine

Mani Srivastava University of California, Los Angeles

Kang L. Wang University of California, Los Angeles

Chi On Chui University of California, Los Angeles

Subramanian S. Iyer University of California, Los Angeles

Lei He University of California, Los Angeles

Suhas Diggavi University of California, Los Angeles

Rajesh Gupta University of California, San Diego

External Links

Personal website of Puneet Gupta Google Scholar page

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