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Electronics and Electrical Engineering

D-Index
53
Citations
11526
World Ranking
2396
National Ranking
929

Materials Science

D-Index
52
Citations
10936
World Ranking
9502
National Ranking
2298

Research.com Recognitions

  • 2017 - Fellow, National Academy of Inventors
  • 2012 - IEEE Daniel E. Noble Award for Emerging Technologies “For the development and implementation of embedded DRAM technologies.”
  • 1995 - IEEE Fellow For contributions to SiGe heterojunction devices and self-aligned silicides.

Overview

Subramanian S. Iyer is affiliated with the University of California, Los Angeles in the United States, with a research focus primarily in the field of Engineering. Their specialization lies within Electrical and Electronic Engineering, complemented by work in Hardware and Architecture, Biomedical Engineering, Computer Networks and Communications, and Electronic, Optical and Magnetic Materials.

The recent scholarly output of this researcher includes studies published in notable venues. Some of the recent papers are:

  • Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration, 2021, IEEE Transactions on Components Packaging and Manufacturing Technology
  • Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors, 2021, IEEE Transactions on Nuclear Science
  • Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding, 2021, ECS Journal of Solid State Science and Technology
  • Recess Effect Study and Process Optimization of Sub-10 μm Pitch Die-to-wafer Hybrid Bonding, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • A Signaling Figure of Merit (s-FoM) for Advanced Packaging, 2020, IEEE Transactions on Components Packaging and Manufacturing Technology

The frequent publication venues where this researcher disseminates their findings include:

  • 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
  • IEEE Transactions on Components Packaging and Manufacturing Technology
  • IEEE Transactions on Nuclear Science
  • ECS Journal of Solid State Science and Technology
  • Science

The main topics covered in the research are:

  • 3D IC and TSV technologies
  • Electronic Packaging and Soldering Technologies
  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Interconnection Networks and Systems

Collaborations have frequently involved several co-authors, demonstrating interdisciplinary and cross-collaborative work. Prominent collaborators include Haoxiang Ren, Yu-Tao Yang, Guangqi Ouyang, Krutikesh Sahoo, and Randall Irwin.

Research contributions have been recognized by professional bodies with several awards. Subramanian S. Iyer has been named a Fellow of the National Academy of Inventors in 2017. Earlier distinctions include the IEEE Daniel E. Noble Award for Emerging Technologies in 2012, awarded for the development and implementation of embedded DRAM technologies. In 1995, they were also named an IEEE Fellow for contributions to SiGe heterojunction devices and self-aligned silicides.

Best Publications

  • Heterojunction bipolar transistors using Si-Ge alloys

    S.S. Iyer;G.L. Patton;J.M.C. Stork;B.S. Meyerson

  • Production of substrate for tensilely strained semiconductor

    Bruce A. Ek;Subramanian Srikanteswara Iyer;Philip Michael Pitner;Adrian R. Powell

  • Light Emission from Silicon

    S. S. Iyer;Y. H. Xie

  • Growth and strain compensation effects in the ternary Si1-x-yGexCy alloy system

    K. Eberl;S. S. Iyer;S. Zollner;J. C. Tsang

  • 3d integrated circuits structure

    Mukta G. Farooq;Subramanian S. Iyer;Steven J. Koester;Huilong Zhu

  • Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxy

    G.L. Patton;S.S. Iyer;S.L. Delage;S. Tiwari

  • New approach to the growth of low dislocation relaxed SiGe material

    A. R. Powell;S. S. Iyer;F. K. LeGoues

  • Electrically programmable fuse (eFUSE) using electromigration in silicides

    C. Kothandaraman;S.K. Iyer;S.S. Iyer

  • DOUBLE POLYSILICON PROCESS FOR PROVIDING SINGLE CHIP HIGH PERFORMANCE LOGIC AND COMPACT EMBEDDED MEMORY STRUCTURE AND RESULTING CHIP STRUCTURE

    Agnello Paul D;Chen Bomy A;Crowder Scott W;Divakaruni Ramachandra

  • Single-etch stop process for the manufacture of silicon-on-insulator wafers

    Subramanian S. Iyer;Emil Baran;Mark L. Mastroianni;Robert A. Craven

  • Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

    N. Robson;J. Safran;C. Kothandaraman;A. Cestero

  • Surface-stress-induced order in SiGe alloy films.

    F. K. LeGoues;V. P. Kesan;S. S. Iyer;J. Tersoff

  • Heterogeneous Integration for Performance and Scaling

    Subramanian S. Iyer

  • Sharp profiles with high and low doping levels in silicon grown by molecular beam epitaxy

    S. S. Iyer;R. A. Metzger;F. G. Allen

  • Growth temperature dependence of interfacial abruptness in Si/Ge heteroepitaxy studied by Raman spectroscopy and medium energy ion scattering

    S. S. Iyer;J. C. Tsang;M. W. Copel;P. R. Pukite

  • Synthesis of Si1−yCy alloys by molecular beam epitaxy

    S. S. Iyer;K. Eberl;M. S. Goorsky;F. K. LeGoues

  • 3D integrated circuit device fabrication with precisely controllable substrate removal

    Mukta G. Farooq;Robert Hannon;Subramanian S. Iyer;Steven J. Koester

  • The kinetics of fast steps on crystal surfaces and its application to the molecular beam epitaxy of silicon

    R. Ghez;S. S. Iyer

  • Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxy

    S.S. Iyer;G.L. Patton;S.S. Delage;S. Tiwari

  • High Temperature Process Limitation on TiSi2

    C. Y. Ting;F. M. d'Heurle;S. S. Iyer;P. M. Fryer

Frequent Co-Authors

Francoise K. LeGoues
Francoise K. LeGoues IBM (United States)
Steven J. Koester
Steven J. Koester University of Minnesota
Johannes M. C. Stork
Johannes M. C. Stork ON Semiconductor (United States)
Mark S. Goorsky
Mark S. Goorsky University of California, Los Angeles
Bernard S. Meyerson
Bernard S. Meyerson IBM (United States)
Sampath Purushothaman
Sampath Purushothaman IBM (United States)
Puneet Gupta
Puneet Gupta University of California, Los Angeles
David L. Harame
David L. Harame IBM (United States)
Gregory G. Freeman
Gregory G. Freeman IBM (United States)
Kangguo Cheng
Kangguo Cheng IBM (United States)

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