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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
72
Citations
25953
World Ranking
793
National Ranking
342

Research.com Recognitions

  • 2009 - IEEE Fellow For contributions to low power digital circuits in deep submicron technology

Overview

Shekhar Borkar is a researcher affiliated with Intel in the United States. Their research contributions span several areas within computer science, with a specific focus on artificial intelligence, hardware and architecture. The core topics of their work include Physical Unclonable Functions (PUFs) and Hardware Security, Security and Verification in Computing, and Cryptographic Implementations and Security.

Their recent publications cover diverse aspects of these fields, including:

  • Security Closure of Physical Layouts ICCAD Special Session Paper, 2021, published in the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
  • IoT-Driven Smart Greenhouse System for Real-Time Environmental Monitoring, 2025, published in the European Journal of Scientific Research and Reviews.
  • Use of machine learning to predict hypertension based on BMI and routine lab data, 2025, published in Bioinformation

Frequent collaborators in their work include Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, and Hussam Amrouch. These coauthors have contributed alongside Borkar in advancing research within the intersection of hardware security and artificial intelligence.

Borkar's scholarly output appears in multiple venues known for disseminating research in computing and interdisciplinary applications, including:

  • 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
  • European Journal of Scientific Research and Reviews.
  • Bioinformation

Their expertise is primarily situated in the field of computer science, particularly within the subfields of artificial intelligence, accounting for two publications, and hardware and architecture, with one publication.

Among their recognitions, Borkar was named an IEEE Fellow in 2009 for contributions to low power digital circuits in deep submicron technology, indicating a notable impact in the area of digital circuit design and power optimization.

Best Publications

  • Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

    S. Borkar

  • Parameter variations and impact on circuits and microarchitecture

    Shekhar Borkar;Tanay Karnik;Siva Narendra;Jim Tschanz

  • Design challenges of technology scaling

    S. Borkar

  • Thousand core chips: a technology perspective

    Shekhar Borkar

  • The future of microprocessors

    Shekhar Borkar;Andrew A. Chien

  • An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

    Sriram R. Vangal;Jason Howard;Gregory Ruhl;Saurabh Dighe

  • A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

    Jason Howard;Saurabh Dighe;Yatin Hoskote;Sriram Vangal

  • Area-efficient linear regulator with ultra-fast load regulation

    Peter Hazucha;Tanay Karnik;Bradley A. Bloechel;Colleen Parsons

  • A 5-GHz Mesh Interconnect for a Teraflops Processor

    Unknown

  • A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

    J Howard;S Dighe;S R Vangal;G Ruhl

  • Technology and design challenges for low power and high performance

    Vivek De;Shekhar Borkar

  • Scaling of stack effect and its application for leakage reduction

    S. Narendra;S. Borkar;V. De;D. Antoniadis

  • Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

    J.W. Tschanz;S.G. Narendra;Y. Ye;B.A. Bloechel

  • A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

    P. Hazucha;G. Schrom;Jaehong Hahn;B.A. Bloechel

  • Near-threshold voltage (NTV) design: opportunities and challenges

    Himanshu Kaul;Mark Anders;Steven Hsu;Amit Agarwal

  • Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

    James Tschanz;Siva Narendra;Zhanping Chen;Shekhar Borkar

  • Thousand Core ChipsA Technology Perspective

    S. Borkar

  • Supporting systolic and memory communication in iWarp

    Shekhar Borkar;Robert Cohn;George Cox;Thomas Gross

  • A sub-130-nm conditional keeper technique

    A. Alvandpour;R.K. Krishnamurthy;K. Soumyanath;S.Y. Borkar

  • A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

    Shailendra Jain;Surhud Khare;Satish Yada;V Ambili

  • Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

    A. Keshavarzi;S. Ma;S. Narendra;B. Bloechel

Frequent Co-Authors

Vivek De
Vivek De Intel (United States)
Ram Krishnamurthy
Ram Krishnamurthy Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Siva G. Narendra
Siva G. Narendra Tyfone, Inc.
Ali Keshavarzi
Ali Keshavarzi Stanford University
Mark A. Anders
Mark A. Anders Intel (United States)
James W. Tschanz
James W. Tschanz Intel (United States)
Sanu Mathew
Sanu Mathew Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Donald S. Gardner
Donald S. Gardner Intel (United States)

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