Ram Krishnamurthy

Research.com Recognitions

• 2011 - IEEE Fellow For contributions to high performance and low power digital circuits for microprocessors

Overview

Best Publications

• Near-threshold voltage (NTV) design: opportunities and challenges

  Himanshu Kaul;Mark Anders;Steven Hsu;Amit Agarwal

  337
  Citations

• 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

  Sanu K. Mathew;Sudhir K. Satpathy;Mark A. Anders;Himanshu Kaul

  312
  Citations

• A sub-130-nm conditional keeper technique

  A. Alvandpour;R.K. Krishnamurthy;K. Soumyanath;S.Y. Borkar

  280
  Citations

• A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

  S. Mathew;M. Anders;R.K. Krishnamurthy;S. Borkar

  219
  Citations

• 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

  S. K. Mathew;S. Srinivasan;M. A. Anders;H. Kaul

  208
  Citations

• A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

  Gregory K. Chen;Raghavan Kumar;H. Ekin Sumbul;Phil C. Knag

  206
  Citations

• 53 Gbps Native ${ m GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

  S K Mathew;F Sheikh;M Kounavis;S Gueron

  170
  Citations

• 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

  Sanu Mathew;Sudhir Satpathy;Vikram Suresh;Mark Anders

  163
  Citations

• Comparison of high-performance VLSI adders in the energy-delay space

  V.G. Oklobdzija;B.R. Zeydel;H.Q. Dao;S. Mathew

  150
  Citations

• High-performance and low-power challenges for sub-70 nm microprocessor circuits

  R.K. Krishnarnurthy;A. Alvandpour;V. De;S. Borkar

  146
  Citations

• A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

  H. Kaul;M.A. Anders;S.K. Mathew;S.K. Hsu

  138
  Citations

• A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

  S.K. Mathew;M.A. Anders;B. Bloechel;Trang Nguyen

  132
  Citations

• An improved unified scalable radix-2 Montgomery multiplier

  D. Harris;R. Krishnamurthy;M. Anders;S. Mathew

  130
  Citations

• A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

  Sudhir Satpathy;Sanu K. Mathew;Vikram Suresh;Mark A. Anders

  116
  Citations

• $\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

  Sanu K. Mathew;David Johnston;Sudhir Satpathy;Vikram Suresh

  113
  Citations

• A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

  C.H. Kim;K. Roy;S. Hsu;R. Krishnamurthy

  112
  Citations

• A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

  S.K. Hsu;S.K. Mathew;M.A. Anders;B.R. Zeydel

  108
  Citations

• Energy-delay estimation technique for high-performance microprocessor VLSI adders

  V.G. Oklobdzija;B.R. Zeydel;H. Dao;S. Mathew

  108
  Citations

• A 130-nm 6-GHz 256 /spl times/ 32 bit leakage-tolerant register file

  R.K. Krishnamurthy;A. Alvandpour;G. Balamurugan;N.R. Shanbhag

  101
  Citations

• Reconfigurable Computing: Architectures, Tools and Applications

  Andreas Koch;Ram Krishnamurthy;John McAllister;Roger Woods

  96
  Citations