2011 - IEEE Fellow For contributions to high performance and low power digital circuits for microprocessors
His primary areas of investigation include CMOS, Electronic engineering, Electrical engineering, Adder and Electronic circuit. His studies deal with areas such as Key generation, Low-power electronics, Integrated circuit, Process variation and Circuit design as well as CMOS. His Electronic engineering research is multidisciplinary, incorporating perspectives in Voltage, Robustness and Leakage.
Ram Krishnamurthy usually deals with Electrical engineering and limits it to topics linked to Random number generation and Feedback loop. His Adder research incorporates themes from Microprocessor, Logic synthesis, 32-bit and Parallel computing. His Electronic circuit research is multidisciplinary, relying on both Floating point, Computation and Binary number.
His scientific interests lie mostly in Electronic engineering, CMOS, Electrical engineering, Computer hardware and Electronic circuit. His Electronic engineering research integrates issues from Transistor, Robustness and Leakage. Ram Krishnamurthy has included themes like Adder, Efficient energy use, Datapath and Very-large-scale integration in his CMOS study.
His Adder research includes elements of Microprocessor and Multiplexer. His Computer hardware study integrates concerns from other disciplines, such as Artificial neural network, Reduction and Cache. His research on Electronic circuit frequently links to adjacent areas such as Low voltage.
The scientist’s investigation covers issues in CMOS, Computer hardware, Voltage, Artificial neural network and Electrical engineering. His CMOS study combines topics in areas such as Logic gate, Efficient energy use, Chip and Parallel computing. Ram Krishnamurthy focuses mostly in the field of Logic gate, narrowing it down to matters related to Electronic circuit and, in some cases, Energy consumption.
His research integrates issues of Electronic engineering, Binary number, Computer data storage and Memory management in his study of Chip. In general Voltage, his work in Node is often linked to Column linking many areas of study. His Electrical engineering study frequently links to related topics such as Power management.
Ram Krishnamurthy focuses on Voltage, Computer hardware, Efficient energy use, Memory array and Artificial intelligence. His work deals with themes such as CMOS, Ideal and Porting, which intersect with Voltage. The various areas that Ram Krishnamurthy examines in his Computer hardware study include Artificial neural network, Software implementation and Range.
The concepts of his Efficient energy use study are interwoven with issues in Floating point, Binary neural network, Electronic engineering and Chip. His Memory array study results in a more complete grasp of Electrical engineering. With his scientific publications, his incorporates both Electrical engineering and Charge.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Near-threshold voltage (NTV) design: opportunities and challenges
Himanshu Kaul;Mark Anders;Steven Hsu;Amit Agarwal.
design automation conference (2012)
A sub-130-nm conditional keeper technique
A. Alvandpour;R.K. Krishnamurthy;K. Soumyanath;S.Y. Borkar.
IEEE Journal of Solid-state Circuits (2002)
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS
Sanu K. Mathew;Sudhir K. Satpathy;Mark A. Anders;Himanshu Kaul.
international solid-state circuits conference (2014)
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core
S. Mathew;M. Anders;R.K. Krishnamurthy;S. Borkar.
IEEE Journal of Solid-state Circuits (2003)
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors
S. K. Mathew;S. Srinivasan;M. A. Anders;H. Kaul.
IEEE Journal of Solid-state Circuits (2012)
53 Gbps Native ${ m GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
S K Mathew;F Sheikh;M Kounavis;S Gueron.
IEEE Journal of Solid-state Circuits (2011)
Comparison of high-performance VLSI adders in the energy-delay space
V.G. Oklobdzija;B.R. Zeydel;H.Q. Dao;S. Mathew.
IEEE Transactions on Very Large Scale Integration Systems (2005)
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
Sanu Mathew;Sudhir Satpathy;Vikram Suresh;Mark Anders.
IEEE Journal of Solid-state Circuits (2015)
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS
H. Kaul;M.A. Anders;S.K. Mathew;S.K. Hsu.
IEEE Journal of Solid-state Circuits (2009)
An improved unified scalable radix-2 Montgomery multiplier
D. Harris;R. Krishnamurthy;M. Anders;S. Mathew.
symposium on computer arithmetic (2005)
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