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Electronics and Electrical Engineering

D-Index
34
Citations
4362
World Ranking
5859
National Ranking
1980

Research.com Recognitions

  • 2018 - IEEE Fellow For leadership in computer arithmetic datapath and security circuits

Overview

Sanu Mathew is affiliated with Intel in the United States and has contributed extensively to research in computer science and engineering. Their research focuses on areas including cryptographic implementations and security, physical unclonable functions (PUFs) and hardware security, as well as chaos-based image and signal encryption.

The scientist's work spans multiple subfields such as artificial intelligence, electrical and electronic engineering, hardware and architecture, computer vision and pattern recognition, and computational theory and mathematics. Research topics also include security and verification in computing, electrostatic discharge in electronics, advancements in semiconductor devices and circuit design, and quantum-dot cellular automata.

Sanu Mathew has published notably in reputable venues, frequently contributing to the following platforms:

  • IEEE Journal of Solid-State Circuits
  • 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • IEEE Solid-State Circuits Letters
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Frequent co-authors collaborating with Sanu Mathew include:

  • Raghavan Kumar
  • Vivek De
  • Vikram Suresh
  • Mark Anders
  • Amit Agarwal

Selected recent publications demonstrate ongoing work related to secure cryptographic hardware:

  • EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing, 2020, IEEE Journal of Solid-State Circuits
  • A 4900-μm2 839-Mb/s Side-Channel Attack-Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition, 2020, IEEE Journal of Solid-State Circuits
  • A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS, 2021, IEEE Journal of Solid-State Circuits
  • An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS, 2022, 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS, 2022, IEEE Journal of Solid-State Circuits

Sanu Mathew was recognized as an IEEE Fellow in 2018 for leadership in computer arithmetic datapath and security circuits.

Best Publications

  • 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

    Sanu K. Mathew;Sudhir K. Satpathy;Mark A. Anders;Himanshu Kaul

  • A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

    S. Mathew;M. Anders;R.K. Krishnamurthy;S. Borkar

  • 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

    S. K. Mathew;S. Srinivasan;M. A. Anders;H. Kaul

  • 53 Gbps Native ${ m GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

    S K Mathew;F Sheikh;M Kounavis;S Gueron

  • 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

    Sanu Mathew;Sudhir Satpathy;Vikram Suresh;Mark Anders

  • Comparison of high-performance VLSI adders in the energy-delay space

    V.G. Oklobdzija;B.R. Zeydel;H.Q. Dao;S. Mathew

  • A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

    H. Kaul;M.A. Anders;S.K. Mathew;S.K. Hsu

  • A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

    S.K. Mathew;M.A. Anders;B. Bloechel;Trang Nguyen

  • An improved unified scalable radix-2 Montgomery multiplier

    D. Harris;R. Krishnamurthy;M. Anders;S. Mathew

  • A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

    Sudhir Satpathy;Sanu K. Mathew;Vikram Suresh;Mark A. Anders

  • $\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

    Sanu K. Mathew;David Johnston;Sudhir Satpathy;Vikram Suresh

  • A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

    S.K. Hsu;S.K. Mathew;M.A. Anders;B.R. Zeydel

  • Energy-delay estimation technique for high-performance microprocessor VLSI adders

    V.G. Oklobdzija;B.R. Zeydel;H. Dao;S. Mathew

  • 16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

    Gregory Chen;Mark A. Anders;Himanshu Kaul;Sudhir K. Satpathy

  • An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

    Sudhir K. Satpathy;Sanu K. Mathew;Raghavan Kumar;Vikram Suresh

  • Sub-500-ps 64-b ALUs in 0.18-/spl mu/m SOI/bulk CMOS: design and scaling trends

    S.K. Mathew;R.K. Krishnamurthy;M.A. Anders;R. Rios

  • A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

    Himanshu Kaul;Mark A. Anders;Sanu K. Mathew;Steven K. Hsu

  • 2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

    Suresh Srinivasan;Sanu Mathew;Rajaraman Ramanarayanan;Farhana Sheikh

  • Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

    Monodeep Kar;Arvind Singh;Sanu K. Mathew;Anand Rajan

  • Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

    Arvind Singh;Monodeep Kar;Sanu K. Mathew;Anand Rajan

  • 8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

    Monodeep Kar;Arvind Singh;Sanu Mathew;Anand Rajan

  • Energy-Delay Estimation Technique for High-Performance Microprocessor

    Vojin G. Oklobdzija;Bart R. Zeydel;Hoang Dao;Sanu Mathew

Frequent Co-Authors

Ram Krishnamurthy
Ram Krishnamurthy Intel (United States)
Mark A. Anders
Mark A. Anders Intel (United States)
Amit Agarwal
Amit Agarwal Indian Institute of Technology Kanpur
Vivek De
Vivek De Intel (United States)
Saibal Mukhopadhyay
Saibal Mukhopadhyay Georgia Institute of Technology
Shekhar Borkar
Shekhar Borkar Qualcomm (United States)
Vojin G. Oklobdzija
Vojin G. Oklobdzija University of California, Davis
James W. Tschanz
James W. Tschanz Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Shreyas Sen
Shreyas Sen Purdue University West Lafayette

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