Sanu Mathew

Sanu Mathew publication distribution in Electronics and Electrical Engineering in 2026

The chart shows the distribution of publications by all Research.com ranked scientists in the field of Electronics and Electrical Engineering in 2026. The highlighted bar marks where Sanu Mathew sits on this spectrum.

Sanu Mathew D-index placement in Electronics and Electrical Engineering in 2026

The chart shows the D-index (discipline H-index) distribution of Electronics and Electrical Engineering scientists ranked by Research.com in 2026. The highlighted bar marks where Sanu Mathew sits on this spectrum.

Research.com Recognitions

• 2018 - IEEE Fellow For leadership in computer arithmetic datapath and security circuits

Overview

Best Publications

• 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

  Sanu K. Mathew;Sudhir K. Satpathy;Mark A. Anders;Himanshu Kaul

  312
  Citations

• A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

  S. Mathew;M. Anders;R.K. Krishnamurthy;S. Borkar

  219
  Citations

• 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

  S. K. Mathew;S. Srinivasan;M. A. Anders;H. Kaul

  208
  Citations

• 53 Gbps Native ${ m GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

  S K Mathew;F Sheikh;M Kounavis;S Gueron

  170
  Citations

• 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

  Sanu Mathew;Sudhir Satpathy;Vikram Suresh;Mark Anders

  163
  Citations

• Comparison of high-performance VLSI adders in the energy-delay space

  V.G. Oklobdzija;B.R. Zeydel;H.Q. Dao;S. Mathew

  150
  Citations

• A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

  H. Kaul;M.A. Anders;S.K. Mathew;S.K. Hsu

  138
  Citations

• A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

  S.K. Mathew;M.A. Anders;B. Bloechel;Trang Nguyen

  132
  Citations

• An improved unified scalable radix-2 Montgomery multiplier

  D. Harris;R. Krishnamurthy;M. Anders;S. Mathew

  130
  Citations

• A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

  Sudhir Satpathy;Sanu K. Mathew;Vikram Suresh;Mark A. Anders

  116
  Citations

• $\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

  Sanu K. Mathew;David Johnston;Sudhir Satpathy;Vikram Suresh

  113
  Citations

• A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

  S.K. Hsu;S.K. Mathew;M.A. Anders;B.R. Zeydel

  108
  Citations

• Energy-delay estimation technique for high-performance microprocessor VLSI adders

  V.G. Oklobdzija;B.R. Zeydel;H. Dao;S. Mathew

  108
  Citations

• 16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

  Gregory Chen;Mark A. Anders;Himanshu Kaul;Sudhir K. Satpathy

  95
  Citations

• An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

  Sudhir K. Satpathy;Sanu K. Mathew;Raghavan Kumar;Vikram Suresh

  91
  Citations

• Sub-500-ps 64-b ALUs in 0.18-/spl mu/m SOI/bulk CMOS: design and scaling trends

  S.K. Mathew;R.K. Krishnamurthy;M.A. Anders;R. Rios

  76
  Citations

• A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

  Himanshu Kaul;Mark A. Anders;Sanu K. Mathew;Steven K. Hsu

  73
  Citations

• 2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

  Suresh Srinivasan;Sanu Mathew;Rajaraman Ramanarayanan;Farhana Sheikh

  72
  Citations

• Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

  Monodeep Kar;Arvind Singh;Sanu K. Mathew;Anand Rajan

  63
  Citations

• Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

  Arvind Singh;Monodeep Kar;Sanu K. Mathew;Anand Rajan

  62
  Citations

• 8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

  Monodeep Kar;Arvind Singh;Sanu Mathew;Anand Rajan

  61
  Citations

• Energy-Delay Estimation Technique for High-Performance Microprocessor

  Vojin G. Oklobdzija;Bart R. Zeydel;Hoang Dao;Sanu Mathew

  8
  Citations