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Computer Science

D-Index
30
Citations
6991
World Ranking
13868
National Ranking
5512

Overview

Alaa R. Alameldeen is a researcher affiliated with Intel in the United States. Their work spans multiple areas within engineering and computer science, focusing particularly on electrical and electronic engineering, artificial intelligence, and signal processing.

Their research contributions include papers published in venues such as arXiv (Cornell University) and IEEE Design and Test. Notable recent publications include:

  • Guest Editors' Introduction: Near-Memory and In-Memory Processing, 2022, IEEE Design and Test
  • AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures, 2025, arXiv (Cornell University)
  • DL-PIM: Improving Data Locality in Processing-in-Memory Systems, 2025, arXiv (Cornell University)

Their research topics cover areas such as:

  • Advanced Memory and Neural Computing
  • Semiconductor Materials and Devices
  • Ferroelectric and Negative Capacitance Devices
  • Security and Verification in Computing
  • Advanced Malware Detection Techniques
  • Radiation Effects in Electronics

Alaa R. Alameldeen has collaborated frequently with other researchers, including Hai Li, Onur Mutlu, Bo Fu, Leo Tenenbaum, and David Gray Adler.

Their work has been featured mainly in the following publication venues:

  • arXiv (Cornell University)
  • IEEE Design and Test

Their main fields of study are:

  • Engineering
  • Computer Science

Subfields of study relevant to their contributions include:

  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Signal Processing

Best Publications

  • Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

    Milo M. K. Martin;Daniel J. Sorin;Bradford M. Beckmann;Michael R. Marty

  • Adaptive Cache Compression for High-Performance Processors

    Alaa R. Alameldeen;David A. Wood

  • Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Chris Wilkerson;Hongliang Gao;Alaa R. Alameldeen;Zeshan Chishti

  • Variability in architectural simulations of multi-threaded workloads

    A.R. Alameldeen;D.A. Wood

  • Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches

    Alaa R. Alameldeen;David A. Wood

  • Estimating the Selectivity of XML Path Expressions for Internet Scale Applications

    Ashraf Aboulnaga;Alaa R. Alameldeen;Jeffrey F. Naughton

  • Reducing cache power with low-cost, multi-bit error-correcting codes

    Chris Wilkerson;Alaa R. Alameldeen;Zeshan Chishti;Wei Wu

  • Improving DRAM performance by parallelizing refreshes with accesses

    Kevin Kai-Wei Chang;Donghyuk Lee;Zeshan Chishti;Alaa R. Alameldeen

  • Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Unknown

  • IPC Considered Harmful for Multiprocessor Workloads

    A.R. Alameldeen;D.A. Wood

  • Improving cache lifetime reliability at ultra-low voltages

    Zeshan Chishti;Alaa R. Alameldeen;Chris Wilkerson;Wei Wu

  • Energy-efficient cache design using variable-strength error-correcting codes

    Alaa R. Alameldeen;Ilya Wagner;Zeshan Chishti;Wei Wu

  • Simulating a $2M commercial server on a $2K PC

    A.R. Alameldeen;M.M.K. Martin;C.J. Mauer;K.E. Moore

  • The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study

    Samira Khan;Donghyuk Lee;Yoongu Kim;Alaa R. Alameldeen

  • Transparent Hardware Management of Stacked DRAM as Part of Memory

    Jaewoong Sim;Alaa R. Alameldeen;Zeshan Chishti;Chris Wilkerson

  • Evaluating Non-deterministic Multi-threaded Commercial Workloads

    Alaa R. Alameldeen;Carl J. Mauer;Min Xu;Pacia J. Harper

  • Adaptive cache compression for high-performance processors

    Unknown

  • Detecting and mitigating data-dependent DRAM failures by exploiting current memory content

    Samira Khan;Chris Wilkerson;Zhe Wang;Alaa R. Alameldeen

  • Improving cache performance using read-write partitioning

    Samira Khan;Alaa R. Alameldeen;Chris Wilkerson;Onur Mutluy

  • Timestamp snooping: an approach for extending SMPs

    Milo M. K. Martin;Daniel J. Sorin;Anastassia Ailamaki;Alaa R. Alameldeen

  • Interactions Between Compression and Prefetching in Chip Multiprocessors

    A.R. Alameldeen;D.A. Wood

  • Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors

    K.A. Bowman;A.R. Alameldeen;S.T. Srinivasan;C.B. Wilkerson

  • Improving DRAM Performance by Parallelizing Refreshes with Accesses

    Kevin K. Chang;Donghyuk Lee;Zeshan Chishti;Alaa R. Alameldeen

Frequent Co-Authors

Chris Wilkerson
Chris Wilkerson Nvidia (United Kingdom)
Shih-Lien Lu
Shih-Lien Lu Washington State University
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Onur Mutlu
Onur Mutlu ETH Zurich
Donghyuk Lee
Donghyuk Lee Nvidia (United States)
Mark D. Hill
Mark D. Hill University of Wisconsin–Madison
Milo M. K. Martin
Milo M. K. Martin Google (United States)
Daniel J. Sorin
Daniel J. Sorin Duke University
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
Glenn J. Hinton
Glenn J. Hinton Intel (United States)

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