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Daniel J. Sorin

Daniel J. Sorin

D-Index & Metrics

Computer Science

D-Index
43
Citations
8549
World Ranking
7939
National Ranking
3421

Research.com Recognitions

  • 2009 - ACM Senior Member

Overview

Daniel J. Sorin is affiliated with Duke University in the United States. Their research primarily spans the fields of Computer Science and Engineering, with a notable focus on subfields such as Computer Networks and Communications, Hardware and Architecture, Electrical and Electronic Engineering, Information Systems, and Aerospace Engineering.

Their scholarly contributions address several main topics of study, including:

  • Parallel Computing and Optimization Techniques
  • Distributed systems and fault tolerance
  • Interconnection Networks and Systems
  • Embedded Systems Design Techniques
  • Advanced Data Storage Technologies
  • Distributed and Parallel Computing Systems
  • Cloud Computing and Resource Management

Some frequent co-authors of Daniel J. Sorin are:

  • Vijay Nagarajan
  • Mark D. Hill
  • David A. Wood
  • David Wood
  • Arya Tschand

Typical publication venues for their work include:

  • Computer
  • arXiv (Cornell University)
  • Synthesis lectures on computer architecture
  • ACM Transactions on Architecture and Code Optimization
  • IEEE Micro

Recent publications by Daniel J. Sorin illustrate a focus on advanced topics in computer architecture and system design. Notable papers include:

  • "A Primer on Memory Consistency and Cache Coherence, Second Edition" (2020), published in Synthesis lectures on computer architecture
  • "Bayesian Optimization for Efficient Accelerator Synthesis" (2020), published in ACM Transactions on Architecture and Code Optimization
  • "Reconfigurable Hardware in Postsilicon Microarchitecture" (2021), published in Computer
  • "Computer Architecture for Orbital Edge Computing" (2020), published in Computer
  • "HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols" (2023), published in IEEE Micro

Daniel J. Sorin has also contributed to book publications, including a work titled A Primer on Memory Consistency and Cache Coherence released in 2020 through Morgan & Claypool Publishers.

In recognition of their professional standing, Daniel J. Sorin became an ACM Senior Member in 2009.

Best Publications

  • Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

    Milo M. K. Martin;Daniel J. Sorin;Bradford M. Beckmann;Michael R. Marty

  • A Primer on Memory Consistency and Cache Coherence

    Daniel J. Sorin;Mark D. Hill;David A. Wood

  • SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery

    Daniel J. Sorin;Milo M. K. Martin;Mark D. Hill;David A. Wood

  • Why on-chip cache coherence is here to stay

    Milo M. K. Martin;Mark D. Hill;Daniel J. Sorin

  • Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

    Albert Meixner;Michael E. Bauer;Daniel Sorin

  • Fault Tolerant Computer Architecture

    Daniel J. Sorin

  • Simulating a $2M commercial server on a $2K PC

    A.R. Alameldeen;M.M.K. Martin;C.J. Mauer;K.E. Moore

  • Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors

    Milo M. K. Martin;Pacia J. Harper;Daniel J. Sorin;Mark D. Hill

  • Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures

    A. Meixner;D.J. Sorin

  • A Primer on Memory Consistency and Cache Coherence: Second Edition

    Vijay Nagarajan;Daniel J. Sorin;Mark D. Hill;David A. Wood

  • Architectures for online error detection and recovery in multicore processors

    Dimitris Gizopoulos;Mihalis Psarakis;Sarita V. Adve;Pradeep Ramachandran

  • Analytic evaluation of shared-memory systems with ILP processors

    Daniel J. Sorin;Vijay S. Pai;Sarita V. Adve;Mary K. Vernon

  • A Mechanism for Online Diagnosis of Hard Faults in Microprocessors

    Fred A. Bower;Daniel J. Sorin;Sule Ozev

  • Multicast snooping: a new coherence method using a multicast address network

    E. Ender Bilir;Ross M. Dickson;Ying Hu;Manoj Plakal

  • Tolerating hard faults in microprocessor array structures

    F.A. Bower;P.G. Shealy;S. Ozev;D.J. Sorin

  • Dynamic power gating with quality guarantees

    Anita Lungu;Pradip Bose;Alper Buyuktosunoglu;Daniel J. Sorin

  • Coset coding to extend the lifetime of memory

    A. N. Jacobvitz;R. Calderbank;D. J. Sorin

  • Robot Motion Planning on a Chip

    Sean Murray;Will Floyd-Jones;Ying Qi;Daniel J. Sorin

  • Evaluating Non-deterministic Multi-threaded Commercial Workloads

    Alaa R. Alameldeen;Carl J. Mauer;Min Xu;Pacia J. Harper

  • Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults

    Bogdan F. Romanescu;Daniel J. Sorin

  • Bandwidth adaptive snooping

    M.M.K. Martin;D.J. Sorin;M.D. Hill;D.A. Wood

Frequent Co-Authors

Mark D. Hill
Mark D. Hill University of Wisconsin–Madison
Milo M. K. Martin
Milo M. K. Martin Google (United States)
Alvin R. Lebeck
Alvin R. Lebeck Duke University
George Konidaris
George Konidaris Brown University
Mary K. Vernon
Mary K. Vernon University of Wisconsin–Madison
Anne Condon
Anne Condon University of British Columbia
Alaa R. Alameldeen
Alaa R. Alameldeen Intel (United States)
Derek L. Eager
Derek L. Eager University of Saskatchewan
Sarita V. Adve
Sarita V. Adve University of Illinois at Urbana-Champaign
Shih-Lien Lu
Shih-Lien Lu Washington State University

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