World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
57
Citations
11943
World Ranking
3873
National Ranking
1832

Electronics and Electrical Engineering

D-Index
57
Citations
11752
World Ranking
1987
National Ranking
779

Research.com Recognitions

  • 2009 - ACM Senior Member
  • 2007 - IEEE Fellow For contributions to power modeling and processor design

Overview

Pradip Bose is affiliated with IBM in the United States and has an extensive research portfolio primarily within the fields of Computer Science and Engineering. Their work spans several subfields including Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Artificial Intelligence, and Information Systems.

The scientist's primary research topics include Parallel Computing and Optimization Techniques, Low-power High-performance VLSI Design, Embedded Systems Design Techniques, Interconnection Networks and Systems, Real-Time Systems Scheduling, Advanced Memory and Neural Computing, and Cloud Computing and Resource Management.

Notable recent publications by Pradip Bose include:

  • Investigating the Effects of Task Scheduling on Thermal Behavior (2024), published in SSRN Electronic Journal
  • A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC (2022), presented at ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference
  • Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles (2021), published in IEEE Computer Architecture Letters
  • Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs (2020), featured in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Reducing Datacenter Compute Carbon Footprint by Harnessing the Power of Specialization: Principles, Metrics, Challenges and Opportunities (2024), published in IEEE Transactions on Semiconductor Manufacturing

Bose frequently collaborates with several co-authors over multiple projects. Prominent among these are Alper Buyuktosunoglu, John-David Wellman, Subhankar Pal, Luca P. Carloni, and Aporva Amarnath.

Their research appears regularly in several publication venues, with multiple contributions to:

  • arXiv (Cornell University)
  • IEEE Computer Architecture Letters
  • IEEE Micro
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Computers

Professional recognition includes being named an ACM Senior Member in 2009 and an IEEE Fellow in 2007 for contributions to power modeling and processor design.

Best Publications

  • An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

    C. Isci;A. Buyuktosunoglu;C.-Y. Chen;P. Bose

  • The impact of technology scaling on lifetime reliability

    J. Srinivasan;S.V. Adve;P. Bose;J.A. Rivers

  • Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

    D.M. Brooks;P. Bose;S.E. Schuster;H. Jacobson

  • Microarchitectural techniques for power gating of execution units

    Zhigang Hu;Alper Buyuktosunoglu;Viji Srinivasan;Victor Zyuban

  • The Case for Lifetime Reliability-Aware Microprocessors

    Jayanth Srinivasan;Sarita V. Adve;Pradip Bose;Jude A. Rivers

  • Addressing failures in exascale computing

    Marc Snir;Robert W Wisniewski;Jacob A Abraham;Sarita V Adve

  • Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

    H.F. Hamann;A. Weger;J.A. Lacey;Zhigang Hu

  • Exploiting Structural Duplication for Lifetime Reliability Enhancement

    Jayanth Srinivasan;Sarita V. Adve;Pradip Bose;Jude A. Rivers

  • Lifetime reliability: toward an architectural solution

    Jayanth Srinivasan;S.V. Adve;Pradip Bose;J.A. Rivers

  • Thermal-aware task scheduling at the system software level

    Jeonghwan Choi;Chen-Yong Cher;Hubertus Franke;Henrdrik Hamann

  • Active Memory Cube: A processing-in-memory architecture for exascale systems

    Ravi Nair;Samuel Antão;Carlo Bertolli;Pradip Bose

  • Dynamically tuning processor resources with adaptive processing

    D.H. Albonesi;R. Balasubramonian;S.G. Dropsbo;S. Dwarkadas

  • SoftArch: an architecture-level tool for modeling and analyzing soft errors

    X. Li;S.V. Adve;Pradip Bose;J.A. Rivers

  • Optimizing pipelines for power and performance

    Viji Srinivasan;David Brooks;Michael Gschwind;Pradip Bose

  • New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors

    D. Brooks;P. Bose;V. Srinivasan;M. K. Gschwind

  • Introducing the Adaptive Energy Management Features of the Power7 Chip

    M Floyd;M Allen-Ware;K Rajamani;B Brock

  • Synchronous interlocked pipelines

    H.M. Jacobson;P.N. Kudva;P. Bose;P.W. Cook

  • Performance analysis and its impact on design

    P. Bose;T.M. Conte

  • Quantifying sources of error in McPAT and potential impacts on architectural studies

    Sam Likun Xi;Hans Jacobson;Pradip Bose;Gu-Yeon Wei

  • A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

    Jeonghee Shin;Victor Zyuban;Pradip Bose;Timothy M. Pinkston

  • Dynamic power gating with quality guarantees

    Anita Lungu;Pradip Bose;Alper Buyuktosunoglu;Daniel J. Sorin

Frequent Co-Authors

Alper Buyuktosunoglu
Alper Buyuktosunoglu IBM (United States)
David Brooks
David Brooks Harvard University
Sarita V. Adve
Sarita V. Adve University of Illinois at Urbana-Champaign
David H. Albonesi
David H. Albonesi Cornell University
Kevin Skadron
Kevin Skadron University of Virginia
Francisco J. Cazorla
Francisco J. Cazorla Barcelona Supercomputing Center
Mircea R. Stan
Mircea R. Stan University of Virginia
Jacob A. Abraham
Jacob A. Abraham The University of Texas at Austin
Mateo Valero
Mateo Valero Barcelona Supercomputing Center
Michael Karl Gschwind
Michael Karl Gschwind IBM (United States)

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