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David H. Albonesi

David H. Albonesi

D-Index & Metrics

Computer Science

D-Index
43
Citations
8975
World Ranking
7903
National Ranking
3410

Electronics and Electrical Engineering

D-Index
41
Citations
8691
World Ranking
4234
National Ranking
1516

Research.com Recognitions

  • 2011 - IEEE Fellow For contributions to power-efficient and adaptive computer architectures

Overview

David H. Albonesi is affiliated with Cornell University in the United States. Their research primarily spans the field of Computer Science with an emphasis on several subfields including Hardware and Architecture, Information Systems, Computer Vision and Pattern Recognition, and Computer Networks and Communications.

The main topics covered in Albonesi's work include Parallel Computing and Optimization Techniques, Cloud Computing and Resource Management, Graph Theory and Algorithms, and Software System Performance and Reliability.

Recent publications by Albonesi are:

  • "Masthead", 2020, IEEE Micro
  • "CuttleSys: Data-Driven Resource Management for Interactive Applications on Reconfigurable Multicores", 2020, arXiv (Cornell University)

Frequent co-authors collaborating with Albonesi include Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Christine A. Shoemaker, Christina Delimitrou, and Lizy K. John.

Albonesi's work has appeared in venues such as arXiv (Cornell University) and IEEE Micro, with multiple publications in both.

In 2011, Albonesi was recognized as an IEEE Fellow for contributions to power-efficient and adaptive computer architectures.

Best Publications

  • Selective Cache Ways: On-Demand Cache Resource Allocation.

    David H. Albonesi

  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

    Rajeev Balasubramonian;David Albonesi;Alper Buyuktosunoglu;Sandhya Dwarkadas

  • Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

    G. Semeraro;G. Magklis;R. Balasubramonian;D.H. Albonesi

  • On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions

    M. Haurylau;Guoqing Chen;Hui Chen;Jidong Zhang

  • Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

    Nevin Kirman;Meyrem Kirman;Rajeev K. Dokania;Jose F. Martinez

  • Reducing the complexity of the register file in dynamic superscalar processors

    Rajeev Balasubramonian;Sandhya Dwarkadas;David H. Albonesi

  • An adaptive issue queue for reduced power at high performance

    Alper Buyuktosunoglu;Stanley Schuster;David Brooks;Pradip Bose

  • Phastlane: a rapid transit optical routing network

    Mark J. Cianchetti;Joseph C. Kerekes;David H. Albonesi

  • Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

    Grigorios Magklis;Michael L. Scott;Greg Semeraro;David H. Albonesi

  • Dynamic frequency and voltage control for a multiple clock domain microarchitecture

    Greg Semeraro;David H. Albonesi;Steven G. Dropsho;Grigorios Magklis

  • Predictions of CMOS compatible on-chip optical interconnect

    Guoqing Chen;Hui Chen;Mikhail Haurylau;Nicholas Nelson

  • Dynamically tuning processor resources with adaptive processing

    D.H. Albonesi;R. Balasubramonian;S.G. Dropsbo;S. Dwarkadas

  • Multiple clock domain microprocessor

    David Albonesi;Greg Semeraro;Grigorios Magklis;Michael L. Scott

  • Scalable thread scheduling and global power management for heterogeneous many-core architectures

    Jonathan A. Winter;David H. Albonesi;Christine A. Shoemaker

  • MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

    Nitish Srivastava;Hanchen Jin;Jie Liu;David Albonesi

  • Dynamically managing the communication-parallelism trade-off in future clustered processors

    Rajeev Balasubramonian;Sandhya Dwarkadas;David H. Albonesi

  • Dynamic IPC/clock rate optimization

    David H. Albonesi

  • Integrating adaptive on-chip storage structures for reduced dynamic power

    S. Dropsho;A. Buyuktosunoglu;R. Balasubramonian;D.H. Albonesi

  • Front-end policies for improved issue efficiency in SMT processors

    A. El-Moursy;D.H. Albonesi

  • Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

    G. Magklis;G. Semeraro;D.H. Albonesi;S.G. Dropsho

Frequent Co-Authors

Sandhya Dwarkadas
Sandhya Dwarkadas University of Rochester
Rajeev Balasubramonian
Rajeev Balasubramonian University of Utah
Alper Buyuktosunoglu
Alper Buyuktosunoglu IBM (United States)
Eby G. Friedman
Eby G. Friedman University of Rochester
Michael L. Scott
Michael L. Scott University of Rochester
Pradip Bose
Pradip Bose IBM (United States)
David Brooks
David Brooks Harvard University
Philippe M. Fauchet
Philippe M. Fauchet Vanderbilt University
Israel Koren
Israel Koren University of Massachusetts Amherst
Christine A. Shoemaker
Christine A. Shoemaker National University of Singapore

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