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Rajeev Balasubramonian

Rajeev Balasubramonian

D-Index & Metrics

Computer Science

D-Index
48
Citations
12104
World Ranking
6084
National Ranking
2739

Research.com Recognitions

  • 2021 - IEEE Fellow For contributions to in-memory computation and memory interface design

Overview

Rajeev Balasubramonian is affiliated with the University of Utah in the United States. Their research spans multiple fields within computer science and engineering, with particular emphasis on areas such as cryptography, data security, semiconductor materials, and advanced memory technologies.

The main fields of study related to their work include:

  • Computer Science
  • Engineering

They have contributed to several subfields, notably:

  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Molecular Biology
  • Communication

Key topics of Rajeev Balasubramonian's research cover:

  • Cryptography and Data Security
  • Complexity and Algorithms in Graphs
  • Semiconductor Materials and Devices
  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Quantum-Dot Cellular Automata
  • Neural Networks and Reservoir Computing

Their recent publications demonstrate a focus on emerging computing technologies, memory architectures, and secure data processing. Notable papers include:

  • "Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion," 2022, IEEE Micro
  • "Efficient Oblivious Query Processing for Range and kNN Queries," 2021, IEEE Transactions on Knowledge and Data Engineering
  • "A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow," 2021, IEEE Transactions on Nanotechnology
  • "XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays," 2023, IEEE Micro
  • "Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract)," 2022, 2022 IEEE 38th International Conference on Data Engineering (ICDE)

Frequent co-authors with whom they have collaborated include:

  • Zhao Chang
  • Dong Xie
  • Feifei Li
  • Jeff M. Phillips
  • Elaine Shi

Rajeev Balasubramonian has published multiple papers in recognized venues such as:

  • IEEE Micro
  • IEEE Transactions on Knowledge and Data Engineering
  • IEEE Transactions on Nanotechnology
  • 2022 IEEE 38th International Conference on Data Engineering (ICDE)

They were recognized as an IEEE Fellow in 2021 for contributions to in-memory computation and memory interface design.

Best Publications

  • ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars

    Ali Shafiee;Anirban Nag;Naveen Muralimanohar;Rajeev Balasubramonian

  • CACTI 6.0: A Tool to Model Large Caches

    Naveen Muralimanohar;Rajeev Balasubramonian;Norman P. Jouppi

  • Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

    Naveen Muralimanohar;Rajeev Balasubramonian;Norm Jouppi

  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

    Rajeev Balasubramonian;David Albonesi;Alper Buyuktosunoglu;Sandhya Dwarkadas

  • Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

    G. Semeraro;G. Magklis;R. Balasubramonian;D.H. Albonesi

  • CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories

    Rajeev Balasubramonian;Andrew B. Kahng;Naveen Muralimanohar;Ali Shafiee

  • Overcoming the challenges of crossbar resistive memory architectures

    Cong Xu;Dimin Niu;Naveen Muralimanohar;Rajeev Balasubramonian

  • Rethinking DRAM design and organization for energy-constrained multi-cores

    Aniruddha N. Udipi;Naveen Muralimanohar;Niladrish Chatterjee;Rajeev Balasubramonian

  • Reducing the complexity of the register file in dynamic superscalar processors

    Rajeev Balasubramonian;Sandhya Dwarkadas;David H. Albonesi

  • NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

    Seth H. Pugsley;Jeffrey Jestes;Huihui Zhang;Rajeev Balasubramonian

  • Micro-pages: increasing DRAM efficiency with locality-aware data placement

    Kshitij Sudan;Niladrish Chatterjee;David Nellans;Manu Awasthi

  • Near-Data Processing: Insights from a MICRO-46 Workshop

    Rajeev Balasubramonian;Jichuan Chang;Troy Manning;Jaime H. Moreno

  • Dynamically tuning processor resources with adaptive processing

    D.H. Albonesi;R. Balasubramonian;S.G. Dropsbo;S. Dwarkadas

  • Multiple clock domain microprocessor

    David Albonesi;Greg Semeraro;Grigorios Magklis;Michael L. Scott

  • Leveraging 3D Technology for Improved Reliability

    Niti Madan;Rajeev Balasubramonian

  • Efficiently prefetching complex address patterns

    Manjunath Shevgoor;Sahil Koladiya;Rajeev Balasubramonian;Chris Wilkerson

  • CHOP: Adaptive filter-based DRAM caching for CMP server platforms

    Xiaowei Jiang;Niti Madan;Li Zhao;Mike Upton

  • Dynamically managing the communication-parallelism trade-off in future clustered processors

    Rajeev Balasubramonian;Sandhya Dwarkadas;David H. Albonesi

  • Handling the problems and opportunities posed by multiple on-chip memory controllers

    Manu Awasthi;David W. Nellans;Kshitij Sudan;Rajeev Balasubramonian

  • Integrating adaptive on-chip storage structures for reduced dynamic power

    S. Dropsho;A. Buyuktosunoglu;R. Balasubramonian;D.H. Albonesi

Frequent Co-Authors

Naveen Muralimanohar
Naveen Muralimanohar Google (United States)
Sandhya Dwarkadas
Sandhya Dwarkadas University of Rochester
David H. Albonesi
David H. Albonesi Cornell University
David Nellans
David Nellans Nvidia (United States)
Norman P. Jouppi
Norman P. Jouppi Google (United States)
Alper Buyuktosunoglu
Alper Buyuktosunoglu IBM (United States)
Michael L. Scott
Michael L. Scott University of Rochester
Feifei Li
Feifei Li Alibaba Group (China)
Pierre-Emmanuel Gaillardon
Pierre-Emmanuel Gaillardon University of Utah
Yan Solihin
Yan Solihin University of Central Florida

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