2026 Naveen Muralimanohar: Computer Science Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Computer Science	33	12405	12043	5030	4803	106	8235

Naveen Muralimanohar publication distribution in Computer Science in 2026

The chart shows the distribution of publications by all Research.com ranked scientists in the field of Computer Science in 2026. The highlighted bar marks where Naveen Muralimanohar sits on this spectrum.

32 publications 991+

This scientist: 106 publications — 10th percentile

10% of scientists in this discipline score the same or lower.

The last bar groups every scientist with 991 publications or more.

Naveen Muralimanohar D-index placement in Computer Science in 2026

The chart shows the D-index (discipline H-index) distribution of Computer Science scientists ranked by Research.com in 2026. The highlighted bar marks where Naveen Muralimanohar sits on this spectrum.

30 D-Index 131+

This scientist: 33 D-Index — 13th percentile

13% of scientists in this discipline score the same or lower.

The last bar groups every scientist with 131 D-Index or more.

Overview

Naveen Muralimanohar is affiliated with Google in the United States. Their professional involvement is situated within the U.S. academic and research environment.

No recent papers, co-authors, or publication venues are listed in the available data, which limits a detailed overview of their specific research contributions or collaboration networks.

There is no information on book publications associated with Naveen Muralimanohar.

Details about main fields of study, subfields, and main topics of work linked to this scientist are not provided in the current data.

There are no recorded awards or honors attributed to Naveen Muralimanohar at this time.

Due to the limited publicly available data on publications, research areas, and achievements, a comprehensive profile cannot elaborate on specific scientific themes or scholarly impact.

Best Publications

ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars

Ali Shafiee;Anirban Nag;Naveen Muralimanohar;Rajeev Balasubramonian

1682
Citations
CACTI 6.0: A Tool to Model Large Caches

Naveen Muralimanohar;Rajeev Balasubramonian;Norman P. Jouppi

1073
Citations
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Naveen Muralimanohar;Rajeev Balasubramonian;Norm Jouppi

778
Citations
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories

Rajeev Balasubramonian;Andrew B. Kahng;Naveen Muralimanohar;Ali Shafiee

478
Citations
Overcoming the challenges of crossbar resistive memory architectures

Cong Xu;Dimin Niu;Naveen Muralimanohar;Rajeev Balasubramonian

371
Citations
Rethinking DRAM design and organization for energy-constrained multi-cores

Aniruddha N. Udipi;Naveen Muralimanohar;Niladrish Chatterjee;Rajeev Balasubramonian

348
Citations
FREE-p: Protecting non-volatile memory against both hard and soft errors

Doe Hyun Yoon;Naveen Muralimanohar;Jichuan Chang;Parthasarathy Ranganathan

255
Citations
CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory

Ke Chen;Sheng Li;Naveen Muralimanohar;Jung Ho Ahn

230
Citations
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Xiangyu Dong;Naveen Muralimanohar;Norm Jouppi;Richard Kaufmann

203
Citations
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support

Xiangyu Dong;Yuan Xie;Naveen Muralimanohar;Norman P. Jouppi

187
Citations
Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Liqun Cheng;Naveen Muralimanohar;Karthik Ramani;Rajeev Balasubramonian

164
Citations
Understanding the trade-offs in multi-level cell ReRAM memory design

Cong Xu;Dimin Niu;Naveen Muralimanohar;Norman P. Jouppi

146
Citations
Architecting Efficient Interconnects for Large Caches with CACTI 6.0

N. Muralimanohar;R. Balasubramonian;N.P. Jouppi

141
Citations
Interconnect design considerations for large NUCA caches

Naveen Muralimanohar;Rajeev Balasubramonian

137
Citations
LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems

Aniruddha N. Udipi;Naveen Muralimanohar;Rajeev Balsubramonian;Al Davis

130
Citations
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories

Hanbin Yoon;Justin Meza;Naveen Muralimanohar;Norman P. Jouppi

119
Citations
Design trade-offs for high density cross-point resistive memory

Dimin Niu;Cong Xu;Naveen Muralimanohar;Norman P. Jouppi

108
Citations
The role of optics in future high radix switch design

Nathan Binkert;Al Davis;Norman P. Jouppi;Moray McLaren

105
Citations
Towards scalable, energy-efficient, bus-based on-chip networks

Aniruddha N. Udipi;Naveen Muralimanohar;Rajeev Balasubramonian

100
Citations
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems

Aniruddha N. Udipi;Naveen Muralimanohar;Rajeev Balasubramonian;Al Davis

93
Citations

Frequent Co-Authors

Norman P. Jouppi Google (United States)

Rajeev Balasubramonian University of Utah

Parthasarathy Ranganathan Google (United States)

Robert Schreiber Cerebras Systems

Paolo Faraboschi Hewlett Packard Enterprise (United States)

Yuan Xie Hong Kong University of Science and Technology

Jung Ho Ahn Seoul National University

Jeffrey C. Mogul Google (United States)

Karthik Ramani Purdue University West Lafayette

R. Stanley Williams Texas A&M University

External Links

Personal website of Naveen Muralimanohar Google Scholar page

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