2019 - Fellow of the American Association for the Advancement of Science (AAAS)
2015 - ACM - IEEE CS Eckert-Mauchly Award For pioneering contributions to the design and analysis of high-performance processors and memory systems.
2014 - Member of the National Academy of Engineering For contributions to the design of computer memory hierarchies.
2006 - ACM Fellow For contributions to the design and analysis of high-performance processors and memory systems.
Norman P. Jouppi mostly deals with Parallel computing, Cache, Embedded system, Multi-core processor and Static random-access memory. His Parallel computing research focuses on Cache coloring, CPU cache, Pipeline, Instruction set and Memory architecture. His Embedded system study combines topics from a wide range of disciplines, such as Non-volatile memory, Computer hardware, Memory controller, Chip and Fault tolerance.
In his work, Multiprocessing, Random access memory and Tag RAM is strongly intertwined with Computer architecture, which is a subfield of Multi-core processor. As a part of the same scientific study, he usually deals with the Static random-access memory, concentrating on Dram and frequently concerns with Universal memory and Memory hierarchy. His studies in Page cache integrate themes in fields like Snoopy cache and MESI protocol.
Norman P. Jouppi spends much of his time researching Computer hardware, Parallel computing, Embedded system, Cache and Artificial intelligence. His Parallel computing research is multidisciplinary, incorporating elements of Thread and Instructions per cycle. His Embedded system research is multidisciplinary, relying on both Dram, Multi-core processor and Chip.
His research in Multi-core processor intersects with topics in Multiprocessing and Computer architecture. All of his Cache and Cache pollution, Cache algorithms and CPU cache investigations are sub-components of the entire Cache study. His Artificial intelligence research focuses on Computer vision and how it relates to Computer graphics.
The scientist’s investigation covers issues in Computer hardware, Parallel computing, Semiconductor memory, Interleaved memory and Cache. The concepts of his Computer hardware study are interwoven with issues in Computation and State. As a member of one scientific family, Norman P. Jouppi mostly works in the field of Parallel computing, focusing on Central processing unit and, on occasion, Multithreading and Execution model.
His Semiconductor memory study integrates concerns from other disciplines, such as Computer architecture and Design space exploration. His work deals with themes such as Registered memory and Embedded system, which intersect with Interleaved memory. His Cache pollution and Cache coloring investigations are all subjects of Cache research.
His primary areas of study are Artificial neural network, Parallel computing, Computer hardware, Throughput and Embedded system. His Parallel computing study frequently draws connections between adjacent fields such as Deep neural networks. His work on Semiconductor memory and Dynamic random-access memory as part of general Computer hardware study is frequently linked to Phase-change memory and Numerical linear algebra, bridging the gap between disciplines.
His Embedded system study combines topics from a wide range of disciplines, such as NAND gate, Logic synthesis and Interleaved memory. His study looks at the relationship between Central processing unit and fields such as Multithreading, as well as how they intersect with chemical problems. His Computer architecture research is multidisciplinary, incorporating perspectives in Multi-core processor, Design space exploration and Cache.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
In-Datacenter Performance Analysis of a Tensor Processing Unit
Norman P. Jouppi;Cliff Young;Nishant Patil;David Patterson.
international symposium on computer architecture (2017)
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
Sheng Li;Jung Ho Ahn;Richard D. Strong;Jay B. Brockman.
international symposium on microarchitecture (2009)
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Norman P. Jouppi.
international symposium on computer architecture (1990)
Complexity-effective superscalar processors
Subbarao Palacharla;Norman P. Jouppi;J. E. Smith.
international symposium on computer architecture (1997)
In-Datacenter Performance Analysis of a Tensor Processing Unit
Norman P. Jouppi;Cliff Young;Nishant Patil;David Patterson.
arXiv: Hardware Architecture (2017)
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
Xiangyu Dong;Cong Xu;Yuan Xie;N. P. Jouppi.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2012)
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
Rakesh Kumar;Keith I. Farkas;Norman P. Jouppi;Parthasarathy Ranganathan.
international symposium on microarchitecture (2003)
CACTI: an enhanced cache access and cycle time model
S.J.E. Wilton;N.P. Jouppi.
IEEE Journal of Solid-state Circuits (1996)
CACTI 6.0: A Tool to Model Large Caches
Naveen Muralimanohar;Rajeev Balasubramonian;Norman P. Jouppi.
(2009)
Corona: System Implications of Emerging Nanophotonic Technology
Dana Vantrease;Robert Schreiber;Matteo Monchiero;Moray McLaren.
international symposium on computer architecture (2008)
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