World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
72
Citations
34297
World Ranking
1637
National Ranking
844

Research.com Recognitions

  • 2010 - ACM Fellow For contributions to distributed microprocessor architectures and memory systems.
  • 2010 - IEEE Fellow For contributions to processor and memory systems
  • 2008 - ACM Distinguished Member
  • 2006 - ACM Senior Member

Overview

Doug Burger is affiliated with Microsoft in the United States and has produced research primarily in the field of Computer Science. Their work spans multiple subfields, including Hardware and Architecture, Artificial Intelligence, Computer Networks and Communications, and Computer Vision and Pattern Recognition.

The scientist has contributed to topics such as Parallel Computing and Optimization Techniques, Embedded Systems Design Techniques, Interconnection Networks and Systems, Advanced Data Compression Techniques, as well as Neural Networks and Reservoir Computing and Applications.

Recent papers authored or co-authored by Doug Burger include:

  • Wavefront Threading Enables Effective High-Level Synthesis, 2024, Proceedings of the ACM on Programming Languages
  • With Shared Microexponents, A Little Shifting Goes a Long Way, 2023, arXiv (Cornell University)
  • Derek Chiou, 2025, IEEE Micro
  • The TRIPS Project, 2025, Communications of the ACM

Frequent co-authors of Doug Burger comprise Blake Pelton, Adam Sapek, Ken Eguro, Daniel Lo, and Alessandro Forin.

Their publications have been featured notably in venues such as Proceedings of the ACM on Programming Languages, arXiv (Cornell University), IEEE Micro, and Communications of the ACM.

Throughout their career, Doug Burger has received several distinctions including IEEE Fellow in 2010 for contributions to processor and memory systems, and ACM Fellow in the same year for contributions to distributed microprocessor architectures and memory systems. They were also named an ACM Distinguished Member in 2008 and an ACM Senior Member in 2006.

Best Publications

  • The SimpleScalar tool set, version 2.0

    Doug Burger;Todd M. Austin

  • Dark silicon and the end of multicore scaling

    Hadi Esmaeilzadeh;Emily Blem;Renee St. Amant;Karthikeyan Sankaralingam

  • Modeling the effect of technology trends on the soft error rate of combinational logic

    P. Shivakumar;M. Kistler;S.W. Keckler;D. Burger

  • Architecting phase change memory as a scalable dram alternative

    Benjamin C. Lee;Engin Ipek;Onur Mutlu;Doug Burger

  • A reconfigurable fabric for accelerating large-scale datacenter services

    Andrew Putnam;Adrian M. Caulfield;Eric S. Chung;Derek Chiou

  • Better I/O through byte-addressable, persistent memory

    Jeremy Condit;Edmund B. Nightingale;Christopher Frost;Engin Ipek

  • An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

    Changkyu Kim;Doug Burger;Stephen W. Keckler

  • Clock rate versus IPC: the end of the road for conventional microarchitectures

    Vikas Agarwal;M. S. Hrishikesh;Stephen W. Keckler;Doug Burger

  • Evaluating future microprocessors : The SimpleScalar tool set

    Doug Burger;Todd M. Austin;Steve Bennett

  • Neural acceleration for general-purpose approximate programs

    Hadi Esmaeilzadeh;Adrian Sampson;Luis Ceze;Doug Burger

  • Exploiting ILP, TLP, and DLP with the polymorphous trips architecture

    K. Sankaralingam;R. Nagarajan;Haiming Liu;Changkyu Kim

  • A NUCA Substrate for Flexible CMP Cache Sharing

    J. Jaehyuk Huh;C. Changkyu Kim;H. Shafi;L. Lixin Zhang

  • Memory Bandwidth Limitations of Future Microprocessors

    Doug Burger;James R. Goodman;Alain Kägi

  • A cloud-scale acceleration architecture

    Adrian M. Caulfield;Eric S. Chung;Andrew Putnam;Hari Angepat

  • A configurable cloud-scale DNN processor for real-time AI

    Jeremy Fowers;Kalin Ovtcharov;Michael Papamichael;Todd Massengill

  • Architecture support for disciplined approximate programming

    Hadi Esmaeilzadeh;Adrian Sampson;Luis Ceze;Doug Burger

  • Phase-Change Technology and the Future of Main Memory

    B.C. Lee;Ping Zhou;Jun Yang;Youtao Zhang

  • Scaling to the end of silicon with EDGE architectures

    D. Burger;S.W. Keckler;K.S. McKinley;M. Dahlin

  • Measuring experimental error in microprocessor simulation

    Rajagopalan Desikan;Doug Burger;Stephen W. Keckler

  • Azure accelerated networking: SmartNICs in the public cloud

    Daniel Firestone;Andrew Putnam;Sambhrama Mundkur;Derek Chiou

  • Dark Silicon and the End of Multicore Scaling

    H. Esmaeilzadeh;E. Blem;R. St. Amant;K. Sankaralingam

  • Memory systems

    Doug Burger

Frequent Co-Authors

Stephen W. Keckler
Stephen W. Keckler Nvidia (United States)
Kathryn S. McKinley
Kathryn S. McKinley Google (United States)
Karthikeyan Sankaralingam
Karthikeyan Sankaralingam University of Wisconsin–Madison
Hadi Esmaeilzadeh
Hadi Esmaeilzadeh University of California, San Diego
Changkyu Kim
Changkyu Kim Facebook (United States)
Karin Strauss
Karin Strauss Microsoft (United States)
Steven K. Reinhardt
Steven K. Reinhardt Advanced Micro Devices (United States)
Eric Horvitz
Eric Horvitz Microsoft (United States)
James R. Larus
James R. Larus École Polytechnique Fédérale de Lausanne
Scott Hauck
Scott Hauck University of Washington

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