2010 - IEEE Fellow For contributions to processor and memory systems
2010 - ACM Fellow For contributions to distributed microprocessor architectures and memory systems.
2008 - ACM Distinguished Member
2006 - ACM Senior Member
Parallel computing, Computer architecture, Embedded system, Dram and Phase-change memory are his primary areas of study. Cache pollution, Cache coloring, Microarchitecture, Cache and Task parallelism are the core of his Parallel computing study. His Microarchitecture research includes themes of Dark silicon, Multi-core processor and Speedup.
The study incorporates disciplines such as TRIPS architecture, Software deployment, Microprocessor, Instruction set and Bandwidth in addition to Computer architecture. His Embedded system study combines topics from a wide range of disciplines, such as Scalability, Distributed memory, Memory hierarchy, Registered memory and Server. His Dram study integrates concerns from other disciplines, such as Memory architecture, Hardware architecture and Operating system.
Doug Burger focuses on Parallel computing, Computer architecture, Microarchitecture, Embedded system and Compiler. His study in Multi-core processor, Cache, Speedup, Instruction set and Instruction-level parallelism is carried out as part of his studies in Parallel computing. His work focuses on many connections between Computer architecture and other disciplines, such as TRIPS architecture, that overlap with his field of interest in Execution model.
His research in Microarchitecture intersects with topics in Microprocessor, Operand and System on a chip. He combines subjects such as Dram, Computer hardware, Scalability, Memory management and Server with his study of Embedded system. His Compiler study combines topics in areas such as Software, Dataflow and Heuristics.
The scientist’s investigation covers issues in Cloud computing, Embedded system, Field-programmable gate array, Encoding and Server. His Cloud computing study is focused on Operating system in general. His study on Reconfigurable computing is often connected to Flow network as part of broader study in Embedded system.
His Field-programmable gate array research is multidisciplinary, incorporating elements of Computer architecture and Latency. The Server study combines topics in areas such as Data center, Hyperscale, Scalability and Resilience. Multi-core processor is closely connected to Network performance in his research, which is encompassed under the umbrella topic of Scalability.
His primary areas of investigation include Cloud computing, Server, Embedded system, Field-programmable gate array and Hyperscale. The various areas that he examines in his Server study include Software and Scalability. His research combines Computer architecture and Field-programmable gate array.
His work deals with themes such as Latency, Compile time, Microservices, System on a chip and SIMD, which intersect with Computer architecture. His Stratix study incorporates themes from Artificial neural network and Microarchitecture. Operating system is represented through his Load balancing and Multi-core processor research.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
The SimpleScalar tool set, version 2.0
Doug Burger;Todd M. Austin.
ACM Sigarch Computer Architecture News (1997)
Dark silicon and the end of multicore scaling
Hadi Esmaeilzadeh;Emily Blem;Renee St. Amant;Karthikeyan Sankaralingam.
international symposium on computer architecture (2011)
Modeling the effect of technology trends on the soft error rate of combinational logic
P. Shivakumar;M. Kistler;S.W. Keckler;D. Burger.
dependable systems and networks (2002)
Architecting phase change memory as a scalable dram alternative
Benjamin C. Lee;Engin Ipek;Onur Mutlu;Doug Burger.
international symposium on computer architecture (2009)
Better I/O through byte-addressable, persistent memory
Jeremy Condit;Edmund B. Nightingale;Christopher Frost;Engin Ipek.
symposium on operating systems principles (2009)
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Changkyu Kim;Doug Burger;Stephen W. Keckler.
architectural support for programming languages and operating systems (2002)
A reconfigurable fabric for accelerating large-scale datacenter services
Andrew Putnam;Adrian M. Caulfield;Eric S. Chung;Derek Chiou.
international symposium on computer architecture (2014)
Clock rate versus IPC: the end of the road for conventional microarchitectures
Vikas Agarwal;M. S. Hrishikesh;Stephen W. Keckler;Doug Burger.
international symposium on computer architecture (2000)
Evaluating future microprocessors : The SimpleScalar tool set
Doug Burger;Todd M. Austin;Steve Bennett.
Technical Report CS-TR-96-1308, University of Wisconsin Madison (1996)
Exploiting ILP, TLP, and DLP with the polymorphous trips architecture
K. Sankaralingam;R. Nagarajan;Haiming Liu;Changkyu Kim.
IEEE Micro (2003)
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