D-Index & Metrics Best Publications

D-Index & Metrics D-index (Discipline H-index) only includes papers and citation values for an examined discipline in contrast to General H-index which accounts for publications across all disciplines.

Discipline name D-index D-index (Discipline H-index) only includes papers and citation values for an examined discipline in contrast to General H-index which accounts for publications across all disciplines. Citations Publications World Ranking National Ranking
Computer Science D-index 63 Citations 19,389 180 World Ranking 1720 National Ranking 942

Research.com Recognitions

Awards & Achievements

2011 - IEEE Fellow For contributions to computer architectures and memory systems

2011 - ACM Fellow For contributions to computer architectures and technology modeling.

2006 - ACM Senior Member

2003 - ACM Grace Murray Hopper Award For ground-breaking analysis of technology scaling for high-performance processors that sheds new light on the methods required to maintain performance improvement trends in computer architecture, and on the design implications for future high-performance processors and systems.

2002 - Fellow of Alfred P. Sloan Foundation

Overview

What is he best known for?

The fields of study he is best known for:

  • Operating system
  • Central processing unit
  • Programming language

Stephen W. Keckler mostly deals with Parallel computing, Computer architecture, Cache, Network on a chip and Microarchitecture. His study in Cache coloring, Cache invalidation, Dataflow, Branch predictor and Task parallelism is done as part of Parallel computing. His research in Dataflow tackles topics such as Convolutional neural network which are related to areas like Artificial neural network and Computer engineering.

The study incorporates disciplines such as TRIPS architecture, Multi-core processor and Graphics processing unit in addition to Computer architecture. His Network on a chip research focuses on Interconnection and how it relates to System on a chip, Electronic design automation and Intelligent Network. He interconnects Microprocessor, Pipeline and Simulation in the investigation of issues within Microarchitecture.

His most cited work include:

  • Modeling the effect of technology trends on the soft error rate of combinational logic (1328 citations)
  • An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (704 citations)
  • Clock rate versus IPC: the end of the road for conventional microarchitectures (595 citations)

What are the main themes of his work throughout his whole career to date?

Stephen W. Keckler mainly focuses on Parallel computing, Computer architecture, Embedded system, Scalability and Cache. His Parallel computing research is multidisciplinary, incorporating elements of Thread and Compiler. His study looks at the relationship between Computer architecture and topics such as TRIPS architecture, which overlap with Instruction set.

He has researched Embedded system in several fields, including Redundancy and Chip. His Scalability research includes themes of Artificial neural network, Computer hardware and Computer network. His work is dedicated to discovering how Cache, Uniform memory access are connected with Registered memory and other disciplines.

He most often published in these fields:

  • Parallel computing (35.45%)
  • Computer architecture (21.69%)
  • Embedded system (17.46%)

What were the highlights of his more recent work (between 2017-2021)?

  • Artificial neural network (9.52%)
  • Artificial intelligence (8.47%)
  • Resilience (4.23%)

In recent papers he was focusing on the following fields of study:

Artificial neural network, Artificial intelligence, Resilience, Parallel computing and Deep learning are his primary areas of study. His work carried out in the field of Artificial neural network brings together such families of science as Scalability, Very-large-scale integration, Dataflow and Computational science. The various areas that Stephen W. Keckler examines in his Resilience study include State, Failure rate, Transient, Fault injection and Convolutional neural network.

His study on Memory bandwidth is often connected to Register file as part of broader study in Parallel computing. His research investigates the connection between Thread and topics such as Multiprocessing that intersect with issues in Speedup and Operand. His research in Bandwidth intersects with topics in Domain, Dram, Cache, Composability and Application domain.

Between 2017 and 2021, his most popular works were:

  • Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks (95 citations)
  • Timeloop: A Systematic Approach to DNN Accelerator Evaluation (72 citations)
  • Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (43 citations)

In his most recent research, the most cited papers focused on:

  • Operating system
  • Central processing unit
  • Programming language

The scientist’s investigation covers issues in Artificial neural network, Software, Deep learning, Artificial intelligence and Reliability engineering. His research integrates issues of Computer hardware and Dataflow in his study of Artificial neural network. His biological study spans a wide range of topics, including Supercomputer, Fault tolerance, Instruction set, Redundancy and Error detection and correction.

His Deep learning research incorporates elements of Backpropagation, Computer architecture, Latency and Virtualization. His studies deal with areas such as Die, Process, Layer, Inference and Speedup as well as Computer architecture. His study in Artificial intelligence is interdisciplinary in nature, drawing from both CUDA and Data structure.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

Modeling the effect of technology trends on the soft error rate of combinational logic

P. Shivakumar;M. Kistler;S.W. Keckler;D. Burger.
dependable systems and networks (2002)

1969 Citations

Modeling the effect of technology trends on the soft error rate of combinational logic

P. Shivakumar;M. Kistler;S.W. Keckler;D. Burger.
dependable systems and networks (2002)

1969 Citations

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Changkyu Kim;Doug Burger;Stephen W. Keckler.
architectural support for programming languages and operating systems (2002)

1047 Citations

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Changkyu Kim;Doug Burger;Stephen W. Keckler.
architectural support for programming languages and operating systems (2002)

1047 Citations

Clock rate versus IPC: the end of the road for conventional microarchitectures

Vikas Agarwal;M. S. Hrishikesh;Stephen W. Keckler;Doug Burger.
international symposium on computer architecture (2000)

991 Citations

Clock rate versus IPC: the end of the road for conventional microarchitectures

Vikas Agarwal;M. S. Hrishikesh;Stephen W. Keckler;Doug Burger.
international symposium on computer architecture (2000)

991 Citations

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

Angshuman Parashar;Minsoo Rhu;Anurag Mukkara;Antonio Puglielli.
international symposium on computer architecture (2017)

812 Citations

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

Angshuman Parashar;Minsoo Rhu;Anurag Mukkara;Antonio Puglielli.
international symposium on computer architecture (2017)

812 Citations

Exploiting ILP, TLP, and DLP with the polymorphous trips architecture

K. Sankaralingam;R. Nagarajan;Haiming Liu;Changkyu Kim.
IEEE Micro (2003)

808 Citations

Exploiting ILP, TLP, and DLP with the polymorphous trips architecture

K. Sankaralingam;R. Nagarajan;Haiming Liu;Changkyu Kim.
IEEE Micro (2003)

808 Citations

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