World's Best Scientists 2026 revealed!
Joel Emer

Joel Emer

D-Index & Metrics

Computer Science

D-Index
72
Citations
33511
World Ranking
1638
National Ranking
845

Research.com Recognitions

  • 2020 - Member of the National Academy of Engineering For quantitative analysis of computer architecture and its application to architectural innovation in commercial microprocessors.
  • 2009 - ACM - IEEE CS Eckert-Mauchly Award For pioneering contributions to performance analysis and modeling methodologies; for design innovations in several significant industry microprocessors; and for deftly bridging research and development, academia and industry.
  • 2004 - ACM Fellow For contributions to computer architecture and performance analysis.
  • 2004 - IEEE Fellow For contributions to computer architecture and quantitative analysis of processor performance.

Overview

Joel Emer is affiliated with MIT in the United States, specializing in fields related to computer science and engineering. Their research portfolio heavily focuses on computer architecture, processor performance analysis, and neural computing technologies.

The scientist has contributed extensively to the literature in areas including:

  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Parallel Computing and Optimization Techniques
  • Advanced Data Storage Technologies
  • Advanced Neural Network Applications
  • CCD and CMOS Imaging Sensors
  • Neural Networks and Reservoir Computing

Main fields of study covered by Joel Emer include:

  • Computer Science
  • Engineering

Subfields of study related to their work include:

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence
  • Computer Vision and Pattern Recognition

Joel Emer's recent published papers reflect a focus on both theoretical and applied aspects of computer systems:

  • "There's plenty of room at the Top: What will drive computer performance after Moore's law?", 2020, Science
  • "Efficient Processing of Deep Neural Networks", 2020, Synthesis lectures on computer architecture
  • "A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm", 2020, IEEE Journal of Solid-State Circuits
  • "How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful", 2020, IEEE Solid-State Circuits Magazine
  • "Simba", 2021, Communications of the ACM

Frequent co-authors collaborating with Joel Emer include:

  • Vivienne Sze
  • Yu-Hsin Chen
  • Tien-Ju Yang
  • Stephen W. Keckler
  • Michael Pellauer

The scientist frequently publishes in venues such as:

  • arXiv (Cornell University)
  • IEEE Journal of Solid-State Circuits
  • IEEE Design and Test
  • IEEE Micro
  • Science

Joel Emer has also contributed to academic books, notably one published by Morgan & Claypool Publishers:

  • Efficient Processing of Deep Neural Networks, 2020

The scientist has received multiple awards throughout their career, such as:

  • Member of the National Academy of Engineering (2020) for quantitative analysis of computer architecture and its application to architectural innovation in commercial microprocessors
  • ACM - IEEE CS Eckert-Mauchly Award (2009) for pioneering contributions to performance analysis, design innovations in industry microprocessors, and bridging research and development
  • IEEE Fellow (2004) for contributions to computer architecture and quantitative analysis of processor performance
  • ACM Fellow (2004) for contributions to computer architecture and performance analysis

Best Publications

  • Efficient Processing of Deep Neural Networks: A Tutorial and Survey

    Vivienne Sze;Yu-Hsin Chen;Tien-Ju Yang;Joel S. Emer

  • Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

    Yu-Hsin Chen;Tushar Krishna;Joel S. Emer;Vivienne Sze

  • 14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

    Yu-Hsin Chen;Tushar Krishna;Joel Emer;Vivienne Sze

  • Eyeriss: a spatial architecture for energy-efficient dataflow for convolutional neural networks

    Yu-Hsin Chen;Joel Emer;Vivienne Sze

  • Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor

    Dean M. Tullsen;Susan J. Eggers;Joel S. Emer;Henry M. Levy

  • A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor

    Shubhendu S. Mukherjee;Christopher Weaver;Joel Emer;Steven K. Reinhardt

  • SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

    Angshuman Parashar;Minsoo Rhu;Anurag Mukkara;Antonio Puglielli

  • Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices

    Yu-Hsin Chen;Tien-Ju Yang;Joel S. Emer;Vivienne Sze

  • Adaptive insertion policies for high performance caching

    Moinuddin K. Qureshi;Aamer Jaleel;Yale N. Patt;Simon C. Steely

  • High performance cache replacement using re-reference interval prediction (RRIP)

    Aamer Jaleel;Kevin B. Theobald;Simon C. Steely;Joel Emer

  • Simultaneous multithreading: a platform for next-generation processors

    S.J. Eggers;J.S. Emer;H.M. Leby;J.L. Lo

  • The soft error problem: an architectural perspective

    S.S. Mukherjee;J. Emer;S.K. Reinhardt

  • Timeloop: A Systematic Approach to DNN Accelerator Evaluation

    Angshuman Parashar;Priyanka Raina;Yakun Sophia Shao;Yu-Hsin Chen

  • Understanding error propagation in deep learning neural network (DNN) accelerators and applications

    Guanpeng Li;Siva Kumar Sastry Hari;Michael Sullivan;Timothy Tsai

  • Memory dependence prediction using store sets

    George Z. Chrysos;Joel S. Emer

  • There’s plenty of room at the Top: What will drive computer performance after Moore’s law?

    Charles E. Leiserson;Neil C. Thompson;Joel S. Emer;Joel S. Emer;Bradley C. Kuszmaul

  • Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

    Kenzo Van Craeynest;Aamer Jaleel;Lieven Eeckhout;Paolo Narvaez

  • Adaptive insertion policies for managing shared caches

    Aamer Jaleel;William Hasenplaugh;Moinuddin Qureshi;Julien Sebot

  • Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

    Jack L. Lo;Joel S. Emer;Henry M. Levy;Rebecca L. Stamm

  • Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

    Christopher Weaver;Joel Emer;Shubhendu S. Mukherjee;Steven K. Reinhardt

  • Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

    Yu-Hsin Chen;Joel S. Emer;Vivienne Sze

  • Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

    Yu-Hsin Chen;Joel Emer;Vivienne Sze

Frequent Co-Authors

Shubhendu S. Mukherjee
Shubhendu S. Mukherjee Cavium (United States)
Aamer Jaleel
Aamer Jaleel Nvidia (United States)
Simon C. Steely
Simon C. Steely Intel (United States)
Stephen W. Keckler
Stephen W. Keckler Nvidia (United States)
Brucek Khailany
Brucek Khailany Nvidia (United States)
William J. Dally
William J. Dally Nvidia (United Kingdom)
Steven K. Reinhardt
Steven K. Reinhardt Advanced Micro Devices (United States)
Yale N. Patt
Yale N. Patt The University of Texas at Austin

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