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D-Index & Metrics

Computer Science

D-Index
36
Citations
7786
World Ranking
11056
National Ranking
4594

Overview

Aamer Jaleel is affiliated with Nvidia in the United States and specializes in research within the field of computer science. Their work spans multiple subfields including artificial intelligence, hardware and architecture, electrical and electronic engineering, computer networks and communications, and aerospace engineering.

Their research topics cover a range of areas focused on computational and engineering challenges. Key topics include:

  • Parallel Computing and Optimization Techniques
  • Security and Verification in Computing
  • Radiation Effects in Electronics
  • Advanced Data Storage Technologies
  • Network Packet Processing and Optimization
  • Guidance and Control Systems
  • VLSI and Analog Circuit Testing

Published works by Aamer Jaleel include both journal and preprint contributions. Recent publications are:

  • "Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation" (2024), published in arXiv (Cornell University)
  • "cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications" (2023), published in Proceedings of the ACM on Programming Languages
  • "Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing" (2023), published in ACM Transactions on Computer Systems
  • "Improving Multi-Instance GPU Efficiency via Sub-Entry Sharing TLB Design" (2024), published in arXiv (Cornell University)
  • "Teaching an Old Dog New Tricks: Verifiable FHE Using Commodity Hardware" (2024), published in arXiv (Cornell University)

Aamer Jaleel frequently collaborates with several researchers, including:

  • Stephen W. Keckler
  • Gururaj Saileshwar
  • Mohamed Tarek Ibn Ziad
  • Sana Damani
  • Mark W. Stephenson

Their work often appears in key venues such as:

  • arXiv (Cornell University)
  • Proceedings of the ACM on Programming Languages
  • ACM Transactions on Computer Systems
  • Proceedings on Privacy Enhancing Technologies

Best Publications

  • Adaptive insertion policies for high performance caching

    Moinuddin K. Qureshi;Aamer Jaleel;Yale N. Patt;Simon C. Steely

  • High performance cache replacement using re-reference interval prediction (RRIP)

    Aamer Jaleel;Kevin B. Theobald;Simon C. Steely;Joel Emer

  • Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

    Kenzo Van Craeynest;Aamer Jaleel;Lieven Eeckhout;Paolo Narvaez

  • DRAMsim: a memory system simulator

    David Wang;Brinda Ganesh;Nuengwong Tuaycharoen;Kathleen Baynes

  • Adaptive insertion policies for managing shared caches

    Aamer Jaleel;William Hasenplaugh;Moinuddin Qureshi;Julien Sebot

  • SHiP: signature-based hit predictor for high performance caching

    Carole-Jean Wu;Aamer Jaleel;Will Hasenplaugh;Margaret Martonosi

  • Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks

    Leonid Domnitser;Aamer Jaleel;Jason Loew;Nael Abu-Ghazaleh

  • CoLT: Coalesced Large-Reach TLBs

    Binh Pham;Viswanathan Vaidyanathan;Aamer Jaleel;Abhishek Bhattacharjee

  • BioBench: A Benchmark Suite of Bioinformatics Applications

    K. Albayraktaroglu;A. Jaleel;X. Wu;M. Franklin

  • ExTensor: An Accelerator for Sparse Tensor Algebra

    Kartik Hegde;Hadi Asghari-Moghaddam;Michael Pellauer;Neal Crago

  • MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability

    Akhil Arunkumar;Evgeny Bolotin;Benjamin Cho;Ugljesa Milic

  • CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

    Chia Chen Chou;Aamer Jaleel;Moinuddin K. Qureshi

  • Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads

    A. Jaleel;M. Mattina;B. Jacob

  • Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies

    Aamer Jaleel;Eric Borch;Malini Bhandaru;Simon C. Steely

  • Analyzing Parallel Programs with Pin

    M. Bach;M. Charney;R. Cohn;E. Demikhovsky

  • PACMan: prefetch-aware cache management for high performance caching

    Carole-Jean Wu;Aamer Jaleel;Margaret Martonosi;Simon C. Steely

  • Triggered instructions: a control paradigm for spatially-programmed architectures

    Angshuman Parashar;Michael Pellauer;Michael Adler;Bushra Ahsan

  • Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

    Seth H Pugsley;Zeshan Chishti;Chris Wilkerson;Peng-fei Chuang

  • A high-resolution side-channel attack on last-level cache

    Mehmet Kayaalp;Dmitry Ponomarev;Nael Abu-Ghazaleh;Aamer Jaleel

  • CRUISE: cache replacement and utility-aware scheduling

    Aamer Jaleel;Hashem H. Najaf-abadi;Samantika Subramaniam;Simon C. Steely

Frequent Co-Authors

Simon C. Steely
Simon C. Steely Intel (United States)
Moinuddin K. Qureshi
Moinuddin K. Qureshi Georgia Institute of Technology
Lieven Eeckhout
Lieven Eeckhout Ghent University
Bruce Jacob
Bruce Jacob University of Maryland, College Park
David Nellans
David Nellans Nvidia (United States)
Nael Abu-Ghazaleh
Nael Abu-Ghazaleh University of California, Riverside
Carole-Jean Wu
Carole-Jean Wu Meta Platforms, Inc.
Dmitry Ponomarev
Dmitry Ponomarev Binghamton University
Yale N. Patt
Yale N. Patt The University of Texas at Austin

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