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D-Index & Metrics

Computer Science

D-Index
39
Citations
8356
World Ranking
9611
National Ranking
4075

Overview

Brucek Khailany is affiliated with Nvidia in the United States. Their research spans multiple domains within computer science and engineering, focusing extensively on areas such as VLSI and FPGA design techniques, parallel computing and optimization techniques, and advanced neural network applications.

Khailany's recent scholarly contributions include:

  • "Accelerating Chip Design With Machine Learning," 2020, IEEE Micro
  • "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm," 2020, IEEE Journal of Solid-State Circuits
  • "ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm," 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Their frequent co-authors are:

  • Haoxing Ren
  • Rangharajan Venkatesan
  • Nathaniel Pinckney
  • Brian Zimmer
  • William J. Dally

Khailany has published in a variety of venues, with notable frequent publication locations including:

  • arXiv (Cornell University)
  • Proceedings of the 59th ACM/IEEE Design Automation Conference
  • 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Journal of Solid-State Circuits

The scientist's work touches on the following main fields of study:

  • Computer Science
  • Engineering

Subfields of study associated with their research include:

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence
  • Industrial and Manufacturing Engineering

Main topics covered in their research are:

  • VLSI and FPGA Design Techniques
  • Parallel Computing and Optimization Techniques
  • Advanced Neural Network Applications
  • Advancements in Photolithography Techniques
  • VLSI and Analog Circuit Testing
  • Ferroelectric and Negative Capacitance Devices
  • Embedded Systems Design Techniques

Best Publications

  • SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

    Angshuman Parashar;Minsoo Rhu;Anurag Mukkara;Antonio Puglielli

  • GPUs and the Future of Parallel Computing

    S. W. Keckler;W. J. Dally;B. Khailany;M. Garland

  • Imagine: media processing with streams

    B. Khailany;W.J. Dally;U.J. Kapasi;P. Mattson

  • Timeloop: A Systematic Approach to DNN Accelerator Evaluation

    Angshuman Parashar;Priyanka Raina;Yakun Sophia Shao;Yu-Hsin Chen

  • Programmable stream processors

    U.J. Kapasi;S. Rixner;W.J. Dally;B. Khailany

  • Register organization for media processing

    S. Rixner;W.J. Dally;B. Khailany;P. Mattson

  • The Imagine Stream Processor

    U.J. Kapasi;W.J. Dally;S. Rixner;J.D. Owens

  • Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

    Yakun Sophia Shao;Jason Clemons;Rangharajan Venkatesan;Brian Zimmer

  • A bandwidth-efficient architecture for media processing

    Scott Rixner;William J. Dally;Ujval J. Kapasi;Brucek Khailany

  • SCNN

    Unknown

  • CudaDMA: optimizing GPU memory bandwidth via warp specialization

    Michael Bauer;Henry Cook;Brucek Khailany

  • Evaluating the Imagine Stream Architecture

    Jung Ho Ahn;William J. Dally;Brucek Khailany;Ujval J. Kapasi

  • DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

    Yibo Lin;Zixuan Jiang;Jiaqi Gu;Wuxi Li

  • Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

    Mark Gebhart;Stephen W. Keckler;Brucek Khailany;Ronny Krashinsky

  • Efficient conditional operations for data-parallel architectures

    Ujval J. Kapasi;William J. Dally;Scott Rixner;Peter R. Mattson

  • A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

    B.K. Khailany;T. Williams;J. Lin;E.P. Long

  • MAGNet: A Modular Accelerator Generator for Neural Networks

    Rangharajan Venkatesan;Priyanka Raina;Yanqing Zhang;Brian Zimmer

  • DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

    Yibo Lin;Shounak Dhar;Wuxi Li;Haoxing Ren

  • Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

    Unknown

  • A bandwidth-efficient architecture for media processing

    Unknown

  • Stream Processors: Progammability and Efficiency: Will this new kid on the block muscle out ASIC and DSP?

    William J. Dally;Ujval J. Kapasi;Brucek Khailany;Jung Ho Ahn

  • High Performance Graph ConvolutionaI Networks with Applications in Testability Analysis

    Yuzhe Ma;Haoxing Ren;Brucek Khailany;Harbinder Sikka

  • SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

    Angshuman Parashar;Minsoo Rhu;Anurag Mukkara;Antonio Puglielli

  • A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

    B. Khailany;T. Williams;J. Lin;E. Long

Frequent Co-Authors

William J. Dally
William J. Dally Nvidia (United Kingdom)
Stephen W. Keckler
Stephen W. Keckler Nvidia (United States)
John D. Owens
John D. Owens University of California, Davis
Scott Rixner
Scott Rixner Rice University
David Z. Pan
David Z. Pan The University of Texas at Austin
Jung Ho Ahn
Jung Ho Ahn Seoul National University
Jiang Hu
Jiang Hu Texas A&M University
Sachin S. Sapatnekar
Sachin S. Sapatnekar University of Minnesota
Anand Raghunathan
Anand Raghunathan Purdue University West Lafayette

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