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Computer Science

D-Index
38
Citations
12161
World Ranking
9967
National Ranking
4193

Overview

Tushar Krishna is affiliated with the Georgia Institute of Technology in the United States. Their work spans multiple aspects of computer science and engineering, with a strong emphasis on hardware architecture and deep learning accelerator design.

Their research includes publications in several key areas such as Parallel Computing and Optimization Techniques, Advanced Neural Network Applications, and Advanced Memory and Neural Computing. Other topics covered include Ferroelectric and Negative Capacitance Devices, Advanced Data Storage Technologies, Stochastic Gradient Optimization Techniques, and Embedded Systems Design Techniques.

Frequent coauthors collaborating with Tushar Krishna include Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Ananda Samajdar, and Sheng-Chun Kao.

They have contributed to a variety of publication venues with several papers appearing in:

  • arXiv (Cornell University)
  • Zenodo (CERN European Organization for Nuclear Research)
  • IEEE Micro
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • ACM Transactions on Architecture and Code Optimization

Notable recent papers authored or coauthored by Tushar Krishna include:

  • MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings (2020, IEEE Micro)
  • Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse (2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
  • Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators (2021, ACM Transactions on Architecture and Code Optimization)
  • Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication (2021, IEEE Transactions on Parallel and Distributed Systems)
  • The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-cores (2025, Zenodo (CERN European Organization for Nuclear Research))

Tushar Krishna has also authored a book titled Data Orchestration in Deep Learning Accelerators published in 2020 by Morgan & Claypool Publishers.

Their main fields of study are Computer Science and Engineering, with significant contributions to several subfields including Electrical and Electronic Engineering, Artificial Intelligence, Hardware and Architecture, Computer Vision and Pattern Recognition, and Computer Networks and Communications.

Best Publications

  • The gem5 simulator

    Nathan Binkert;Bradford Beckmann;Gabriel Black;Steven K. Reinhardt

  • GARNET: A detailed on-chip network model inside a full-system simulator

    Niket Agarwal;Tushar Krishna;Li-Shiuan Peh;Niraj K. Jha

  • SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training

    Eric Qin;Ananda Samajdar;Hyoukjun Kwon;Vineet Nadella

  • MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects

    Hyoukjun Kwon;Ananda Samajdar;Tushar Krishna

  • Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach

    Hyoukjun Kwon;Prasanth Chatarasi;Michael Pellauer;Angshuman Parashar

  • SCALE-Sim: Systolic CNN Accelerator Simulator

    Ananda Samajdar;Yuhao Zhu;Paul Whatmough;Matthew Mattina

  • A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim

    Ananda Samajdar;Jan Moritz Joseph;Yuhao Zhu;Paul Whatmough

  • MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings

    Hyoukjun Kwon;Prasanth Chatarasi;Vivek Sarkar;Tushar Krishna

  • SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering

    Bhavya K. Daya;Chia-Hsin Owen Chen;Suvinay Subramanian;Woo-Cheol Kwon

  • SMART: a single-cycle reconfigurable NoC for SoC applications

    Chia-Hsin Owen Chen;Sunghyun Park;Tushar Krishna;Suvinay Subramanian

  • Breaking the on-chip latency barrier using SMART

    Unknown

  • Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

    Sunghyun Park;Tushar Krishna;Chia-Hsin Chen;Bhavya Daya

  • Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks

    Lei Yang;Zheyu Yan;Meng Li;Hyoukjun Kwon

  • Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

    Tushar Krishna;Li-Shiuan Peh;Bradford M. Beckmann;Steven K. Reinhardt

  • ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning

    Sheng-Chun Kao;Geonhwa Jeong;Tushar Krishna

  • Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices

    Ramyad Hadidi;Jiashen Cao;Yilun Xie;Bahar Asgari

  • NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication

    T. Krishna;A. Kumar;P. Chiang;M. Erez

  • Heterogeneous Dataflow Accelerators for Multi-DNN Workloads

    Hyoukjun Kwon;Liangzhen Lai;Michael Pellauer;Tushar Krishna

  • GAMMA: automating the HW mapping of DNN models on accelerators via genetic algorithm

    Sheng-Chun Kao;Tushar Krishna

  • Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

    Jinwoo Kim;Gauthaman Murali;Heechun Park;Eric Qin

  • SCALE-Sim: Systolic CNN Accelerator.

    Ananda Samajdar;Yuhao Zhu;Paul N. Whatmough;Matthew Mattina

  • The gem5 Simulator: Version 20.0+

    Jason Lowe-Power;Abdul Ahmad;Adria Armejach;Adrian Herrera

Frequent Co-Authors

Sung Kyu Lim
Sung Kyu Lim Georgia Institute of Technology
Hyesoon Kim
Hyesoon Kim Georgia Institute of Technology
Vivek Sarkar
Vivek Sarkar Georgia Institute of Technology
Eduard Alarcon
Eduard Alarcon Universitat Politècnica de Catalunya
Natalie Enright Jerger
Natalie Enright Jerger University of Toronto
Rainer Leupers
Rainer Leupers RWTH Aachen University
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology
Madhavan Swaminathan
Madhavan Swaminathan Pennsylvania State University
Saibal Mukhopadhyay
Saibal Mukhopadhyay Georgia Institute of Technology
Xiaoli Ma
Xiaoli Ma Georgia Institute of Technology

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