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Marian Verhelst

Marian Verhelst

D-Index & Metrics

Computer Science

D-Index
41
Citations
6144
World Ranking
8924
National Ranking
88

Electronics and Electrical Engineering

D-Index
39
Citations
5950
World Ranking
4721
National Ranking
102

Overview

Marian Verhelst is affiliated with KU Leuven in Belgium and conducts research primarily in the fields of Computer Science and Engineering. Their work spans several subfields, including Electrical and Electronic Engineering, Hardware and Architecture, Artificial Intelligence, Computer Vision and Pattern Recognition, and Computer Networks and Communications.

The scientist's research covers a range of topics focused on advanced computing and system design. Key areas of study include Advanced Memory and Neural Computing, Parallel Computing and Optimization Techniques, CCD and CMOS Imaging Sensors, Advanced Neural Network Applications, Ferroelectric and Negative Capacitance Devices, Embedded Systems Design Techniques, and Interconnection Networks and Systems.

Marian Verhelst has frequently published in notable venues including:

  • arXiv (Cornell University)
  • IEEE Journal of Solid-State Circuits
  • IEEE Solid-State Circuits Magazine
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Among their recent significant publications are:

  • Benchmarking TinyML Systems: Challenges and Direction, 2020, arXiv (Cornell University)
  • ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators, 2021, IEEE Transactions on Computers
  • Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-μW Keyword Spotting and Speaker Verification, 2020, IEEE Journal of Solid-State Circuits
  • A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS, 2020, IEEE Journal of Solid-State Circuits
  • DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC, 2022, 2022 IEEE International Solid-State Circuits Conference (ISSCC)

Collaboration is a notable aspect of their work, with frequent coauthors including Linyan Mei, Arne Symons, Vikram Jain, Pouya Houshmand, and Man Shi.

Best Publications

  • 14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI

    Bert Moons;Roel Uytterhoeven;Wim Dehaene;Marian Verhelst

  • An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

    Daniel Bankman;Lita Yang;Bert Moons;Marian Verhelst

  • A Review on Internet of Things Solutions for Intelligent Energy Control in Buildings for Smart City Applications

    Iman Khajenasiri;Abouzar Estebsari;Marian Verhelst;Georges Gielen

  • Benchmarking TinyML Systems: Challenges and Direction

    Colby R. Banbury;Vijay Janapa Reddi;Max Lam;William Fu

  • An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

    Bert Moons;Marian Verhelst

  • A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

    Bert Moons;Marian Verhelst

  • Embedded Deep Neural Network Processing: Algorithmic and Processor Techniques Bring Deep Learning to IoT and Edge Devices

    Marian Verhelst;Bert Moons

  • Minimum energy quantized neural networks

    Bert Moons;Koen Goetschalckx;Nick Van Berckelaer;Marian Verhelst

  • Energy-efficient ConvNets through approximate computing

    Bert Moons;Bert De Brabandere;Luc Van Gool;Marian Verhelst

  • ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators

    Linyan Mei;Pouya Houshmand;Vikram Jain;Sebastian Giraldo

  • An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

    Daniel Bankman;Lita Yang;Bert Moons;Marian Verhelst

  • A 90 nm CMOS, $6\ {\upmu { ext{W}}}$ Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection

    Komail M. H. Badami;Steven Lauwereins;Wannes Meert;Marian Verhelst

  • A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

    A. Ravi;P. Madoglio;Hongtao Xu;K. Chandrashekar

  • Where Analog Meets Digital: Analog?to?Information Conversion and Beyond

    Marian Verhelst;Ahmad Bahai

  • DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC

    Unknown

  • The SINS database for detection of daily activities in a home environment using an Acoustic Sensor Network

    Gert Dekkers;Steven Lauwereins;Bart Thoen;Mulu Weldegebreal Adhana

  • BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS

    Bert Moons;Daniel Bankman;Lita Yang;Boris Murmann

  • Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing

    Vincent Camus;Linyan Mei;Christian Enz;Marian Verhelst

  • Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- $\mu$ W Keyword Spotting and Speaker Verification

    Juan Sebastian P. Giraldo;Steven Lauwereins;Komail Badami;Marian Verhelst

  • A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

    J. Ryckaert;M. Verhelst;M. Badaroglu;S. D'Amico

  • Energy-Efficiency and Accuracy of Stochastic Computing Circuits in Emerging Technologies

    Bert Moons;Marian Verhelst

  • A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

    N. Van Helleputte;M. Verhelst;W. Dehaene;G. Gielen

  • A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

    Athanasios T. Ramkaj;Juan C. Pena Ramos;Marcel J. M. Pelgrom;Michiel S. J. Steyaert

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