Jae-sun Seo

Overview

Best Publications

• Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

  Naveen Suda;Vikas Chandra;Ganesh Dasika;Abinash Mohanty

  643
  Citations

• XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

  Shihui Yin;Zhewei Jiang;Jae-Sun Seo;Mingoo Seok

  467
  Citations

• A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

  Jae-sun Seo;Bernard Brezzo;Yong Liu;Benjamin D. Parker

  449
  Citations

• Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

  Yufei Ma;Yu Cao;Sarma Vrudhula;Jae-sun Seo

  409
  Citations

• Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

  Yufei Ma;Yu Cao;Sarma Vrudhula;Jae-sun Seo

  349
  Citations

• Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

  Chetan Singh Thakur;Jamal Lottier Molin;Gert Cauwenberghs;Giacomo Indiveri

  270
  Citations

• C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

  Zhewei Jiang;Shihui Yin;Jae-Sun Seo;Mingoo Seok

  265
  Citations

• XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

  Xiaoyu Sun;Shihui Yin;Xiaochen Peng;Rui Liu

  236
  Citations

• Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

  Yufei Ma;Naveen Suda;Yu Cao;Jae-sun Seo

  196
  Citations

• Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems

  B. Rajendran;Yong Liu;Jae-sun Seo;K. Gopalakrishnan

  191
  Citations

• Fully parallel write/read in resistive synaptic array for accelerating on-chip learning.

  Ligang Gao;I-Ting Wang;Pai-Yu Chen;Sarma Vrudhula

  157
  Citations

• XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

  Zhewei Jiang;Shihui Yin;Mingoo Seok;Jae-sun Seo

  152
  Citations

• Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning

  Pai-Yu Chen;Binbin Lin;I-Ting Wang;Tuo-Hung Hou

  151
  Citations

• An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks

  Yufei Ma;Yu Cao;Sarma Vrudhula;Jae-sun Seo

  146
  Citations

• Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions

  Arindam Basu;Jyotibdha Acharya;Tanay Karnik;Huichu Liu

  134
  Citations

• High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS

  Shihui Yin;Xiaoyu Sun;Shimeng Yu;Jae-sun Seo

  129
  Citations

• ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

  Yufei Ma;Naveen Suda;Yu Cao;Sarma B. K. Vrudhula

  100
  Citations

• Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

  Pai-Yu Chen;Deepak Kadetotad;Zihan Xu;Abinash Mohanty

  81
  Citations

• Reconfigurable and customizable general-purpose circuits for neural networks

  Bernard V. Brezzo;Leland Chang;Steven K. Esser;Daniel J. Friedman

  79
  Citations

• A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference

  Unknown

  79
  Citations

• Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

  Shihui Yin;Jae-sun Seo;Yulhwa Kim;Xu Han

  69
  Citations

• A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

  Jongwoo Lee;J. Kang;Sunghyun Park;Jae-sun Seo

  68
  Citations

• High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

  Shihui Yin;Xiaoyu Sun;Shimeng Yu;Jae-Sun Seo

  27
  Citations