His scientific interests lie mostly in CMOS, Electrical engineering, Optoelectronics, MOSFET and Electronic engineering. Leland Chang has included themes like Neuromorphic engineering, Electronic circuit, Nanoelectronics and Integrated circuit in his CMOS study. The various areas that Leland Chang examines in his Electrical engineering study include Planar and System on a chip.
His Optoelectronics research is multidisciplinary, incorporating perspectives in Layer, Phonon and Transistor. His MOSFET research integrates issues from Electron mobility, Leakage, PMOS logic, Silicon on insulator and Gate oxide. The Static random-access memory and Logic gate research Leland Chang does as part of his general Electronic engineering study is frequently linked to other disciplines of science, such as CPU cache, therefore creating a link between diverse domains of science.
Leland Chang mainly investigates Optoelectronics, Electrical engineering, Electronic engineering, Condensed matter physics and CMOS. The concepts of his Optoelectronics study are interwoven with issues in Layer, Gate oxide and MOSFET. The MOSFET study combines topics in areas such as Threshold voltage, Planar and Leakage.
His work deals with themes such as Substrate and Communication channel, which intersect with Electrical engineering. Leland Chang has included themes like Power, Electronic circuit and Integrated circuit in his Electronic engineering study. His work in CMOS addresses issues such as Static random-access memory, which are connected to fields such as Low voltage, Embedded system and Node.
Leland Chang mainly focuses on Electrical engineering, Electronic engineering, CMOS, Static random-access memory and Transistor. His Electrical engineering research incorporates themes from Power and Optoelectronics. The study incorporates disciplines such as Substrate and Gate stack in addition to Optoelectronics.
His study looks at the intersection of Electronic engineering and topics like Electronic circuit with Signal. His research integrates issues of Integrated circuit design, Neuromorphic engineering and Microelectromechanical systems in his study of CMOS. His Transistor study integrates concerns from other disciplines, such as Schottky diode, Silicon on insulator and Line.
Leland Chang focuses on CMOS, Electronic engineering, Computer hardware, Electrical engineering and Static random-access memory. CMOS is a subfield of Optoelectronics that Leland Chang studies. His work in Optoelectronics tackles topics such as Layer which are related to areas like Planar, Second source, Semiconductor and Communication channel.
His Logic gate study in the realm of Electronic engineering connects with subjects such as Piecewise. Transistor is the focus of his Electrical engineering research. His biological study spans a wide range of topics, including Low voltage, Integrated circuit design and Content-addressable memory.
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Variational calculations on a quantum well in an electric field
G. Bastard;E. E. Mendez;L. L. Chang;L. Esaki.
Physical Review B (1983)
New Transport Phenomenon in a Semiconductor "Superlattice"
L. Esaki;L. L. Chang.
Physical Review Letters (1974)
Sub 50-nm FinFET: PMOS
Xuejue Huang;Wen-Chin Lee;Charles Kuo;D. Hisamoto.
international electron devices meeting (1999)
Stable SRAM cell design for the 32 nm node and beyond
L. Chang;D.M. Fried;J. Hergenrother;J.W. Sleight.
symposium on vlsi technology (2005)
FinFET scaling to 10 nm gate length
Bin Yu;Leland Chang;S. Ahmed;Haihong Wang.
international electron devices meeting (2002)
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu;Tsu-Jae King;Vivek Subramanian;Leland Chang.
Sub-50 nm P-channel FinFET
Xuejue Huang;Wen-Chin Lee;C. Kuo;D. Hisamoto.
IEEE Transactions on Electron Devices (2001)
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
L. Chang;R.K. Montoye;Y. Nakamura;K.A. Batson.
IEEE Journal of Solid-state Circuits (2008)
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Jae-sun Seo;Bernard Brezzo;Yong Liu;Benjamin D. Parker.
custom integrated circuits conference (2011)
Extremely scaled silicon nano-CMOS devices
L. Chang;Yang-kyu Choi;D. Ha;P. Ranade.
Proceedings of the IEEE (2003)
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