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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
39
Citations
6660
World Ranking
4680
National Ranking
80

Research.com Recognitions

  • 1994 - IEEE Fellow For contributions to high-performance bipolar devices, circuits, and technology.

Overview

Ching-Te Chuang is affiliated with National Yang Ming Chiao Tung University in Taiwan. Their research spans multiple fields including Engineering, Computer Science, and Materials Science, with notable focus in subfields such as Electronic, Optical and Magnetic Materials, Inorganic Chemistry, Electrical and Electronic Engineering, Mechanical Engineering, and Computer Vision and Pattern Recognition.

Their main research topics include:

  • Supercapacitor Materials and Fabrication
  • Metal-Organic Frameworks: Synthesis and Applications
  • Chaos-based Image/Signal Encryption
  • Cryptographic Implementations and Security
  • Advanced Malware Detection Techniques
  • Advanced Battery Technologies Research
  • Electronic Packaging and Soldering Technologies

Chuang has published in various venues, some of which include:

  • IEEE Access
  • Electrochimica Acta
  • The International Journal of Advanced Manufacturing Technology
  • ACS Applied Materials & Interfaces

Recent publications include:

  • Hardware Implementation of High-Throughput S-Box in AES for Information Security, 2023, IEEE Access
  • Mesopore matters: Hierarchically porous metal-organic framework with facilitated redox-hopping and electrochemical behaviors toward the use in supercapacitors, 2025, Electrochimica Acta
  • Investigation of ultrasonic joining parameters affecting the joining quality of Cu wire to Cu pads in lithium battery electrical circuits, 2025, The International Journal of Advanced Manufacturing Technology
  • Mesopores in Metal-Organic Frameworks Rendering Enhanced Rate Capability of Pore-Confined Polyaniline for Supercapacitors, 2025, ACS Applied Materials & Interfaces

Frequent co-authors include:

  • Yu-Chi Wang
  • Ya-Mei Weng
  • Cheng-Yan Hsieh
  • Hsin-Ya Tsai
  • Kuan-Chu Wu

Ching-Te Chuang was honored as an IEEE Fellow in 1994 for contributions to high-performance bipolar devices, circuits, and technology.

Best Publications

  • Turning silicon on its edge [double gate CMOS/FinFET technology]

    E.J. Nowak;I. Aller;T. Ludwig;K. Kim

  • Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

    Ming-Hsien Tu;Jihi-Yu Lin;Ming-Chien Tsai;Shyh-Jye Jou

  • 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

    Yi Wei Chiu;Yu Hao Hu;Ming Hsien Tu;Jun Kai Zhao

  • The impact of gate-oxide breakdown on SRAM stability

    R. Rodriguez;J.H. Stathis;B.P. Linder;S. Kowalczyk

  • Design and CAD Challenges in sub-90nm CMOS Technologies

    Kerry Bernstein;Ching-Te Chuang;Rajiv Joshi;Ruchir Puri

  • High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

    Meng-Hsueh Chiang;Keunwoo Kim;Ching-Te Chuang;C. Tretz

  • Floating-body effects in partially depleted SOI CMOS circuits

    Pong-Fei Lu;Ching-Te Chuang;Jin Ji;L.F. Wagner

  • Novel Cu-to-Cu Bonding With Ti Passivation at 180 $^{\circ}{ m C}$ in 3-D Integration

    Yan-Pin Huang;Yu-San Chien;Ruoh-Ning Tzeng;Ming-Shaw Shy

  • Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

    Aditya Bansal;Rahul M. Rao;Jae-Joon Kim;Sufi Zafar

  • Analysis of the settling behavior of an operational amplifier

    Unknown

  • A 400 MHz S/390 microprocessor

    C.F. Webb;C.J. Anderson;L. Sigal;K.L. Shepard

  • SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

    Saibal Mukhopadhyay;Rahul M Rao;Jae-Joon Kim;Ching-Te Chuang

  • Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM

    Hao-I Yang;Shyh-Chyi Yang;Wei Hwang;Ching-Te Chuang

  • High-performance SRAM in nanoscale CMOS: Design challenges and techniques

    Ching-Te Chuang;S. Mukhopadhyay;Jae-Joon Kim;Keunwoo Kim

  • Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

    Saibal Mukhopadhyay;Keunwoo Kim;K.A. Jenkins;Ching-Te Chuang

  • A thin-membrane surface-acoustic-wave vapor-sensing device

    C.T. Chuang;R.M. White;J.J. Bernstein

  • A submicrometer high-performance bipolar technology

    T.-C. Chen;K.Y. Toh;J.D. Cressler;J. Warnock

  • Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell

    R.V. Joshi;S. Mukhopadhyay;D.W. Plass;Y.H. Chan

  • Novel high-density low-power logic circuit techniques using DG devices

    Meng-Hsueh Chiang;Keunwoo Kim;C. Tretz;Ching-Te Chuang

  • Nanoscale CMOS circuit leakage power reduction by double-gate device

    Keunwoo Kim;Koushik K. Das;Rajiv V. Joshi;Ching-Te Chuang

  • Floating body effects in partially-depleted SOI CMOS circuits

    P. Lu;J. Ji;C. Chuang;L. Wagner

  • A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders

    Unknown

Frequent Co-Authors

Kuan-Neng Chen
Kuan-Neng Chen National Yang Ming Chiao Tung University
Kaushik Roy
Kaushik Roy Purdue University West Lafayette
Saibal Mukhopadhyay
Saibal Mukhopadhyay Georgia Institute of Technology
John D. Cressler
John D. Cressler Georgia Institute of Technology
Tak H. Ning
Tak H. Ning IBM (United States)
James H. Stathis
James H. Stathis IBM (United States)
Keith A. Jenkins
Keith A. Jenkins IBM (United States)
Jeffrey W. Sleight
Jeffrey W. Sleight IBM (United States)
Sufi Zafar
Sufi Zafar IBM (United States)
Ghavam G. Shahidi
Ghavam G. Shahidi IBM (United States)

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