2003 - ACM Fellow For contributions to low power design and testing of digital systems.
The scientist’s investigation covers issues in Embedded system, Electronic engineering, Scheduling, Software and Energy consumption. His Embedded system research includes themes of Distributed computing, Operating system, Low-power electronics and Dynamic voltage scaling. Particularly relevant to Logic synthesis is his body of work in Electronic engineering.
He has researched Scheduling in several fields, including Pipeline, High-level synthesis and Hardware software. His work carried out in the field of Energy consumption brings together such families of science as Security service, Cryptographic protocol, Cryptography, Real-time computing and Computer network. His study explores the link between Electronic circuit and topics such as CMOS that cross with problems in Transistor and Leakage.
Niraj K. Jha mainly investigates Embedded system, Electronic engineering, Electronic circuit, Algorithm and CMOS. The study incorporates disciplines such as Energy consumption and Software, Operating system, Embedded software in addition to Embedded system. His Electronic engineering research is multidisciplinary, incorporating elements of Integrated circuit, Electrical engineering and Leakage.
His Algorithm research incorporates themes from Fault tolerance, Design for testing and Fault coverage. His CMOS study incorporates themes from Node, Control reconfiguration, Circuit design and Test set. As a part of the same scientific study, Niraj K. Jha usually deals with the Application-specific integrated circuit, concentrating on High-level synthesis and frequently concerns with Distributed computing and Computer engineering.
His primary areas of study are Artificial intelligence, Artificial neural network, Wearable computer, Machine learning and Inference. His studies in Artificial intelligence integrate themes in fields like Redundancy and Pattern recognition. Niraj K. Jha has included themes like Wireless, Health care, Computer security, Real-time computing and Decision support system in his Wearable computer study.
Niraj K. Jha works mostly in the field of Distributed computing, limiting it down to concerns involving Network architecture and, occasionally, Energy consumption. In his work, Embedded system is strongly intertwined with Computer network, which is a subfield of Communication channel. He interconnects Transistor and Integrated circuit in the investigation of issues within Embedded system.
His primary areas of investigation include Artificial intelligence, Artificial neural network, Wearable computer, Machine learning and Pattern recognition. The Artificial intelligence study combines topics in areas such as Redundancy and Information system. His studies deal with areas such as Network planning and design, Deep learning, Bayesian optimization and Reinforcement learning as well as Artificial neural network.
The various areas that Niraj K. Jha examines in his Wearable computer study include Wireless, Health care, Computer security, Enhanced Data Rates for GSM Evolution and Real-time computing. His Latency research is multidisciplinary, relying on both Scalability, Multi-core processor and Embedded system. Niraj K. Jha performs multidisciplinary study in Embedded system and Context in his work.
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Switching and Finite Automata Theory
Zvi Kohavi;Niraj K. Jha.
GARNET: A detailed on-chip network model inside a full-system simulator
Niket Agarwal;Tushar Krishna;Li-Shiuan Peh;Niraj K. Jha.
international symposium on performance analysis of systems and software (2009)
Dynamic voltage scaling with links for power optimization of interconnection networks
Li Shang;Li-Shiuan Peh;N.K. Jha.
high-performance computer architecture (2003)
A Comprehensive Study of Security of Internet-of-Things
Arsalan Mosenia;Niraj K. Jha.
IEEE Transactions on Emerging Topics in Computing (2017)
Express virtual channels: towards the ideal interconnection fabric
Amit Kumar;Li-Shiuan Peh;Partha Kundu;Niraj K. Jha.
international symposium on computer architecture (2007)
A study of the energy consumption characteristics of cryptographic algorithms and security protocols
N.R. Potlapally;S. Ravi;A. Raghunathan;N.K. Jha.
IEEE Transactions on Mobile Computing (2006)
Testing of Digital Systems
Niraj K. Jha;Sandeep Gupta.
An Algorithm for Synthesis of Reversible Logic Circuits
P. Gupta;A. Agrawal;N.K. Jha.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2006)
Analyzing the energy consumption of security protocols
Nachiketh R. Potlapally;Srivaths Ravi;Anand Raghunathan;Niraj K. Jha.
international symposium on low power electronics and design (2003)
High-Level Power Analysis and Optimization
Anand Raghunathan;Niraj K. Jha;Sujit Dey.
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