1987 - IEEE Fellow For contributions to the design of testable digital logic circuits and fault-tolerant computing.
Sudhakar M. Reddy spends much of his time researching Algorithm, Electronic engineering, Sequential logic, Automatic test pattern generation and Fault. Sudhakar M. Reddy combines subjects such as Set, Benchmark, Fault coverage and Fault detection and isolation with his study of Algorithm. As a member of one scientific family, Sudhakar M. Reddy mostly works in the field of Fault coverage, focusing on Stuck-at fault and, on occasion, Fault indicator.
His study in Electronic engineering is interdisciplinary in nature, drawing from both Electronic circuit and Voltage. Sudhakar M. Reddy works mostly in the field of Automatic test pattern generation, limiting it down to concerns involving Very-large-scale integration and, occasionally, Computer hardware. His Fault research integrates issues from Function, Real-time computing, System testing and Test set.
Sudhakar M. Reddy mostly deals with Algorithm, Automatic test pattern generation, Fault coverage, Fault and Sequential logic. His Algorithm research incorporates themes from Test, Electronic circuit, Stuck-at fault, Fault detection and isolation and Test set. The various areas that Sudhakar M. Reddy examines in his Electronic circuit study include Electronic engineering, Logic gate, Computer engineering and Benchmark.
In Automatic test pattern generation, Sudhakar M. Reddy works on issues like Scan chain, which are connected to Boundary scan. In his research, Testability is intimately related to Design for testing, which falls under the overarching field of Fault coverage. His Sequential logic study combines topics from a wide range of disciplines, such as Compaction, Asynchronous circuit, Logic testing, Logic optimization and Sequence.
The scientist’s investigation covers issues in Algorithm, Automatic test pattern generation, Fault coverage, Electronic circuit and Logic gate. He has included themes like Test, Fault, Stuck-at fault, Fault detection and isolation and Test set in his Algorithm study. As part of one scientific family, he deals mainly with the area of Fault detection and isolation, narrowing it down to issues related to the Real-time computing, and often Built-in self-test.
His work focuses on many connections between Automatic test pattern generation and other disciplines, such as Test data, that overlap with his field of interest in Volume. Sudhakar M. Reddy interconnects Reliability engineering, Very-large-scale integration, Sequential logic and Test method in the investigation of issues within Fault coverage. His study looks at the intersection of Electronic circuit and topics like Parallel computing with Graph theory.
The scientist’s investigation covers issues in Automatic test pattern generation, Algorithm, Logic gate, Electronic circuit and Electronic engineering. The concepts of his Automatic test pattern generation study are interwoven with issues in System on a chip, Computer engineering, Fault coverage and Boolean satisfiability problem. The study incorporates disciplines such as Reliability engineering, Very-large-scale integration, Hamming distance and Control theory in addition to Fault coverage.
His work deals with themes such as Fault, Stuck-at fault, Fault detection and isolation, Real-time computing and Test set, which intersect with Algorithm. His Electronic circuit research includes themes of Point and Parallel computing, Benchmark. His Electronic engineering study integrates concerns from other disciplines, such as Steady state, Resistive touchscreen, Low-power electronics and Voltage.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
COMPACTEST: a method to generate compact test sets for combinational circuits
I. Pomeranz;L.N. Reddy;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)
On Delay Fault Testing in Logic Circuits
Chin Jen Lin;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1987)
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers (1972)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1995)
Techniques for minimizing power dissipation in scan and combinational circuits during test application
V. Dabholkar;S. Chakravarty;I. Pomeranz;S. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1998)
On determining scan flip-flops in partial-scan designs
D.H. Lee;S.M. Reddy.
international conference on computer aided design (1990)
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
Santiago Remersaro;Xijiang Lin;Zhuo Zhang;Sudhakar Reddy.
international test conference (2006)
On test data volume reduction for multiple scan chain designs
Sudhakar M. Reddy;Kohei Miyase;Seiji Kajihara;Irith Pomeranz.
ACM Transactions on Design Automation of Electronic Systems (2003)
Distributed fault-tolerance for large multiprocessor systems
J. G. Kuhl;S. M. Reddy.
international symposium on computer architecture (1980)
On n-detection test sets and variable n-detection test sets for transition faults
I. Pomeranz;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2000)
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