H-Index & Metrics Top Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Computer Science H-index 60 Citations 14,336 457 World Ranking 1526 National Ranking 852
Electronics and Electrical Engineering H-index 53 Citations 9,643 306 World Ranking 921 National Ranking 432

Research.com Recognitions

Awards & Achievements

1987 - IEEE Fellow For contributions to the design of testable digital logic circuits and fault-tolerant computing.

Overview

What is he best known for?

The fields of study he is best known for:

  • Algorithm
  • Statistics
  • Programming language

Sudhakar M. Reddy spends much of his time researching Algorithm, Electronic engineering, Sequential logic, Automatic test pattern generation and Fault. Sudhakar M. Reddy combines subjects such as Set, Benchmark, Fault coverage and Fault detection and isolation with his study of Algorithm. As a member of one scientific family, Sudhakar M. Reddy mostly works in the field of Fault coverage, focusing on Stuck-at fault and, on occasion, Fault indicator.

His study in Electronic engineering is interdisciplinary in nature, drawing from both Electronic circuit and Voltage. Sudhakar M. Reddy works mostly in the field of Automatic test pattern generation, limiting it down to concerns involving Very-large-scale integration and, occasionally, Computer hardware. His Fault research integrates issues from Function, Real-time computing, System testing and Test set.

His most cited work include:

  • On Delay Fault Testing in Logic Circuits (522 citations)
  • Techniques for minimizing power dissipation in scan and combinational circuits during test application (311 citations)
  • Easily Testable Realizations ror Logic Functions (259 citations)

What are the main themes of his work throughout his whole career to date?

Sudhakar M. Reddy mostly deals with Algorithm, Automatic test pattern generation, Fault coverage, Fault and Sequential logic. His Algorithm research incorporates themes from Test, Electronic circuit, Stuck-at fault, Fault detection and isolation and Test set. The various areas that Sudhakar M. Reddy examines in his Electronic circuit study include Electronic engineering, Logic gate, Computer engineering and Benchmark.

In Automatic test pattern generation, Sudhakar M. Reddy works on issues like Scan chain, which are connected to Boundary scan. In his research, Testability is intimately related to Design for testing, which falls under the overarching field of Fault coverage. His Sequential logic study combines topics from a wide range of disciplines, such as Compaction, Asynchronous circuit, Logic testing, Logic optimization and Sequence.

He most often published in these fields:

  • Algorithm (58.88%)
  • Automatic test pattern generation (42.93%)
  • Fault coverage (37.01%)

What were the highlights of his more recent work (between 2008-2020)?

  • Algorithm (58.88%)
  • Automatic test pattern generation (42.93%)
  • Fault coverage (37.01%)

In recent papers he was focusing on the following fields of study:

The scientist’s investigation covers issues in Algorithm, Automatic test pattern generation, Fault coverage, Electronic circuit and Logic gate. He has included themes like Test, Fault, Stuck-at fault, Fault detection and isolation and Test set in his Algorithm study. As part of one scientific family, he deals mainly with the area of Fault detection and isolation, narrowing it down to issues related to the Real-time computing, and often Built-in self-test.

His work focuses on many connections between Automatic test pattern generation and other disciplines, such as Test data, that overlap with his field of interest in Volume. Sudhakar M. Reddy interconnects Reliability engineering, Very-large-scale integration, Sequential logic and Test method in the investigation of issues within Fault coverage. His study looks at the intersection of Electronic circuit and topics like Parallel computing with Graph theory.

Between 2008 and 2020, his most popular works were:

  • At-speed scan test with low switching activity (69 citations)
  • Modeling and Mitigating Transient Errors in Logic Circuits (33 citations)
  • Definition and generation of partially-functional broadside tests (33 citations)

In his most recent research, the most cited papers focused on:

  • Algorithm
  • Statistics
  • Programming language

The scientist’s investigation covers issues in Automatic test pattern generation, Algorithm, Logic gate, Electronic circuit and Electronic engineering. The concepts of his Automatic test pattern generation study are interwoven with issues in System on a chip, Computer engineering, Fault coverage and Boolean satisfiability problem. The study incorporates disciplines such as Reliability engineering, Very-large-scale integration, Hamming distance and Control theory in addition to Fault coverage.

His work deals with themes such as Fault, Stuck-at fault, Fault detection and isolation, Real-time computing and Test set, which intersect with Algorithm. His Electronic circuit research includes themes of Point and Parallel computing, Benchmark. His Electronic engineering study integrates concerns from other disciplines, such as Steady state, Resistive touchscreen, Low-power electronics and Voltage.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Top Publications

On Delay Fault Testing in Logic Circuits

Chin Jen Lin;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1987)

703 Citations

Easily Testable Realizations ror Logic Functions

S.M. Reddy.
IEEE Transactions on Computers (1972)

464 Citations

COMPACTEST: a method to generate compact test sets for combinational circuits

I. Pomeranz;L.N. Reddy;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)

445 Citations

Techniques for minimizing power dissipation in scan and combinational circuits during test application

V. Dabholkar;S. Chakravarty;I. Pomeranz;S. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1998)

373 Citations

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1995)

320 Citations

On determining scan flip-flops in partial-scan designs

D.H. Lee;S.M. Reddy.
international conference on computer aided design (1990)

293 Citations

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

S. Remersaro;X. Lin;Z. Zhang;S.M. Reddy.
international test conference (2006)

289 Citations

Distributed fault-tolerance for large multiprocessor systems

J. G. Kuhl;S. M. Reddy.
international symposium on computer architecture (1980)

279 Citations

On path selection in combinational logic circuits

Wing-Ning Li;S.M. Reddy;S.K. Sahni.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1989)

218 Citations

On the detection of delay faults

A.K. Pramanick;S.M. Reddy.
international test conference (1988)

217 Citations

Profile was last updated on December 6th, 2021.
Research.com Ranking is based on data retrieved from the Microsoft Academic Graph (MAG).
The ranking h-index is inferred from publications deemed to belong to the considered discipline.

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