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Sudhakar M. Reddy

Sudhakar M. Reddy

D-Index & Metrics

Computer Science

D-Index
73
Citations
20130
World Ranking
1598
National Ranking
831

Electronics and Electrical Engineering

D-Index
69
Citations
18471
World Ranking
962
National Ranking
405

Research.com Recognitions

  • 1987 - IEEE Fellow For contributions to the design of testable digital logic circuits and fault-tolerant computing.

Overview

Sudhakar M. Reddy is affiliated with the University of Iowa in the United States. Their research contributions have been recognized in the field of digital logic design and fault-tolerant computing.

In 1987, Sudhakar M. Reddy was awarded the IEEE Fellow distinction for contributions to the design of testable digital logic circuits and fault-tolerant computing. This award reflects their involvement in advancing methodologies related to reliable and testable hardware systems.

Best Publications

  • COMPACTEST: a method to generate compact test sets for combinational circuits

    I. Pomeranz;L.N. Reddy;S.M. Reddy

  • On Delay Fault Testing in Logic Circuits

    Chin Jen Lin;S.M. Reddy

  • Easily Testable Realizations ror Logic Functions

    S.M. Reddy

  • Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

    S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy

  • Techniques for minimizing power dissipation in scan and combinational circuits during test application

    V. Dabholkar;S. Chakravarty;I. Pomeranz;S. Reddy

  • On determining scan flip-flops in partial-scan designs

    D.H. Lee;S.M. Reddy

  • Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

    Santiago Remersaro;Xijiang Lin;Zhuo Zhang;Sudhakar Reddy

  • Distributed fault-tolerance for large multiprocessor systems

    J. G. Kuhl;S. M. Reddy

  • On test data volume reduction for multiple scan chain designs

    Sudhakar M. Reddy;Kohei Miyase;Seiji Kajihara;Irith Pomeranz

  • On n-detection test sets and variable n-detection test sets for transition faults

    I. Pomeranz;S.M. Reddy

  • On path selection in combinational logic circuits

    Wing-Ning Li;S.M. Reddy;S.K. Sahni

  • On the detection of delay faults

    A.K. Pramanick;S.M. Reddy

  • 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits

    I. Pomeranz;S.M. Reddy

  • A Low Power Pseudo-Random BIST Technique

    Nadir Z. Basturkmen;Sudhakar M. Reddy;Irith Pomeranz

  • Application processing and decision systems and processes

    Sandeep Gupta;Christian Hall;James Reid;Shen Lu

  • New binary codes

    N. Sloane;S. Reddy;Chin-Long Chen

  • Convolutional compaction of test responses

    J. Rajski;J. Tyszer;Chen Wang;S.M. Reddy

  • Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm

    Yu Huang;S.M. Reddy;Wu-Tung Cheng;P. Reuter

  • On static compaction of test sequences for synchronous sequential circuits

    Irith Pomeranz;Sudhakar M. Reddy

  • FAULT-DIAGNOSIS IN FULLY DISTRIBUTED SYSTEMS

    J.G. Kuhl;S.M. Reddy

  • 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set

    I. Pomeranz;S.M. Reddy

Frequent Co-Authors

Irith Pomeranz
Irith Pomeranz Purdue University West Lafayette
Wu-Tung Cheng
Wu-Tung Cheng Mentor Graphics
Janusz Rajski
Janusz Rajski Siemens (Germany)
Bernd Becker
Bernd Becker University of Freiburg
Sandip Kundu
Sandip Kundu University of Massachusetts Amherst
Seiji Kajihara
Seiji Kajihara Kyushu Institute of Technology
Ilia Polian
Ilia Polian University of Stuttgart
Bashir M. Al-Hashimi
Bashir M. Al-Hashimi King's College London
Kewal K. Saluja
Kewal K. Saluja University of Wisconsin–Madison
Jerzy Tyszer
Jerzy Tyszer Poznań University of Technology

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