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Vishwani D. Agrawal

Vishwani D. Agrawal

D-Index & Metrics

Computer Science

D-Index
60
Citations
14863
World Ranking
3226
National Ranking
1566

Electronics and Electrical Engineering

D-Index
60
Citations
14486
World Ranking
1626
National Ranking
658

Research.com Recognitions

  • 2002 - ACM Fellow For contributions to testing of digital electronic circuits.
  • 1986 - IEEE Fellow For contributions to probabilistic testing techniques for large integrated circuits.

Overview

Vishwani D. Agrawal is affiliated with Auburn University in the United States. Their research primarily focuses on areas related to electronic testing, integrated circuits, and hardware security.

The scientist has contributed to multiple publications in various venues, with a significant number appearing in the Journal of Electronic Testing. Other publication venues include the International Journal of Research Publication and Reviews, Lecture Notes in Networks and Systems, and the International Scientific Journal of Engineering and Management.

Recent papers published by Vishwani D. Agrawal include:

  • Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures, 2020, Journal of Electronic Testing
  • Estimating Operational Age of an Integrated Circuit, 2021, Journal of Electronic Testing
  • A Survey and Recent Advances: Machine Intelligence in Electronic Testing, 2024, Journal of Electronic Testing
  • Editorial, 2021, Journal of Electronic Testing
  • Editorial, 2021, Journal of Electronic Testing

Frequent coauthors who have collaborated with Vishwani D. Agrawal include:

  • Soham Roy
  • Spencer K. Millican
  • Brandon Stiene
  • Prattay Chowdhury
  • Ujjwal Guin

The main fields and subfields of study linked to this scientist's research focus on:

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Software
  • Control and Systems Engineering

Key research topics covered in their work include:

  • Integrated Circuits and Semiconductor Failure Analysis
  • VLSI and Analog Circuit Testing
  • Software Testing and Debugging Techniques
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Semiconductor Materials and Devices
  • Engineering and Test Systems
  • Computational Physics and Python Applications

Vishwani D. Agrawal has received awards recognizing their contributions to the field of electronic testing. These include being named an IEEE Fellow in 1986 for contributions to probabilistic testing techniques for large integrated circuits, and an ACM Fellow in 2002 for contributions to testing of digital electronic circuits.

Best Publications

  • Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

    M. Bushnell;Vishwani Agrawal

  • A partial scan method for sequential circuits with feedback

    K.-T. Cheng;V.D. Agrawal

  • A tutorial on built-in self-test. I. Principles

    V.D. Agrawal;C.R. Kime;K.K. Saluja

  • An exact algorithm for selecting partial scan flip-flops

    Srimat T. Chakradhar;Arun Balakrishnan;Vishwani D. Agrawal

  • Scheduling tests for VLSI systems under power constraints

    R.M. Chou;K.K. Saluja;V.D. Agrawal

  • A tutorial on built-in self-test. 2. Applications

    V.D. Agrawal;C.R. Kime;K.K. Saluja

  • Single Event Upset: An Embedded Tutorial

    Fan Wang;V.D. Agrawal

  • Design of a dichroic Cassegrain subreflector

    V. Agrawal;W. Imbriale

  • Chip Layout Optimization Using Critical Path Weighting

    A. E. Dunlop;V. D. Agrawal;D. N. Deutsch;M. F. Jukl

  • A transitive closure algorithm for test generation

    S.T. Chakradhar;V.D. Agrawal;S.G. Rothweiler

  • Statistical Fault Analysis

    Sunil K. Jain;Vishwani D. Agrawal

  • Designing circuits with partial scan

    V.D. Agrawal;Kwang-Ting Cheng;D.D. Johnson;T. Sheng Lin

  • Test Generation for MOS Circuits Using D-Algorithm

    Sunil K. Jain;Vishwani D. Agrawal

  • Fault coverage requirement in production testing of LSI circuits

    V.D. Agrawal;S.C. Seth;P. Agrawal

  • Segment delay faults: a new fault model

    K. Heragu;J.H. Patel;V.D. Agrawal

  • An economical scan design for sequential logic test generation

    K.-T. Cheng;V.D. Agrawal

  • A directed search method for test generation using a concurrent simulator

    V.D. Agrawal;Kwang-Ting Cheng;P. Agrawal

  • Tutorial test generation for VLSI chips

    Vishwani D. Agrawal;Sharad C. Seth

  • Delay fault models and test generation for random logic sequential circuits

    T. J. Chakraborty;V. D. Agrawal;M. L. Bushnell

  • Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests

    Marwan A. Gharaybeh;Michael L. Bushnell;Vishwani D. Agrawal

Frequent Co-Authors

Srimat T. Chakradhar
Srimat T. Chakradhar NEC (United States)
Prathima Agrawal
Prathima Agrawal Auburn University
Kwang-Ting Cheng
Kwang-Ting Cheng Hong Kong University of Science and Technology
Kewal K. Saluja
Kewal K. Saluja University of Wisconsin–Madison
Janak H. Patel
Janak H. Patel University of Illinois at Urbana-Champaign
Michael S. Hsiao
Michael S. Hsiao Virginia Tech
Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
John W. Lockwood
John W. Lockwood Algo-Logic Systems
Miron Abramovici
Miron Abramovici Broadcom (United States)

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