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Computer Science

D-Index
48
Citations
10747
World Ranking
6124
National Ranking
140

Electronics and Electrical Engineering

D-Index
47
Citations
10575
World Ranking
3175
National Ranking
86

Overview

Matteo Sonza Reorda is affiliated with the Polytechnic University of Turin in Italy. Their research primarily spans the fields of Computer Science and Engineering, with a particular focus on Electrical and Electronic Engineering and Hardware and Architecture. Their work also engages with subfields such as Software, Artificial Intelligence, and Computer Networks and Communications.

Their research topics cover a range of specialized areas including:

  • Radiation Effects in Electronics
  • VLSI and Analog Circuit Testing
  • Parallel Computing and Optimization Techniques
  • Integrated Circuits and Semiconductor Failure Analysis
  • Advanced Neural Network Applications
  • Adversarial Robustness in Machine Learning
  • Software Testing and Debugging Techniques

Matteo Sonza Reorda has published extensively in various venues. Their frequent publication venues include:

  • Electronics
  • IEEE Access
  • arXiv (Cornell University)
  • Microelectronics Reliability
  • IEEE Design and Test

Some recent papers illustrating their research contributions are:

  • "Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey," 2022, IEEE Access
  • "FlexGripPlus: An improved GPGPU model to support reliability analysis," 2020, Microelectronics Reliability
  • "Characterizing a Neutron-Induced Fault Model for Deep Neural Networks," 2022, IEEE Transactions on Nuclear Science
  • "Multilevel Simulation Methodology for FMECA Study Applied to a Complex Cyber-Physical System," 2020, Electronics
  • "An On-Line Testing Technique for the Scheduler Memory of a GPGPU," 2020, IEEE Access

Their frequent co-authors include:

  • Josie E. Rodriguez Condia
  • Juan-David Guerrero-Balaguera
  • Robert Limas Sierra
  • Riccardo Cantoro
  • Fernando Fernandes dos Santos

Best Publications

  • RT-level ITC'99 benchmarks and first ATPG results

    F. Corno;M.S. Reorda;G. Squillero

  • Microprocessor Software-Based Self-Testing

    Mihalis Psarakis;Dimitris Gizopoulos;Ernesto Sanchez;Matteo Sonza Reorda

  • Soft-error detection using control flow assertions

    O. Goloubeva;M. Rebaudengo;M. Sonza Reorda;M. Violante

  • On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

    F.L. Kastensmidt;L. Sterpone;L. Carro;M.S. Reorda

  • Soft-error detection through software fault-tolerance techniques

    M. Rebaudengo;M. Sonza Reorda;M. Torchiano;M. Violante

  • Software-Implemented Hardware Fault Tolerance

    Olga Goloubeva;Maurizio Rebaudengo;Matteo Sonza Reorda;Massimo Violante

  • Automatic test program generation: a case study

    F. Corno;E. Sanchez;M.S. Reorda;G. Squillero

  • GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

    F. Corno;P. Prinetto;M. Rebaudengo;M. Sonza Reorda

  • Low power BIST via non-linear hybrid cellular automata

    F. Corno;M. Rebaudengo;M.S. Reorda;G. Squillero

  • A test pattern generation methodology for low power consumption

    E. Corno;P. Prinetto;M. Rebaudengo;M.S. Reorda

  • A source-to-source compiler for generating dependable software

    M. Rebaudengo;M.S. Reorda;M. Violante;M. Torchiano

  • An automatic test pattern generator for large sequential circuits based on Genetic Algorithms

    P. Prinetto;M. Rebaudengo;M. Sonza Reorda

  • Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

    M. Bellato;P. Bernardi;D. Bortolato;A. Candelori

  • An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits

    P. Civera;L. Macchiarulo;M. Rebaudengo;M. Sonza Reorda

  • Exploiting circuit emulation for fast hardness evaluation

    P. Civera;L. Macchiarulo;M. Rebaudengo;M.S. Reorda

  • Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

    Heather Quinn;William H. Robinson;Paolo Rech;Miguel Aguirre

  • On the test of microprocessor IP cores

    F. Corno;M. Sonza Reorda;G. Squillero;M. Violante

  • A new hybrid fault detection technique for systems-on-a-chip

    P. Bernardi;L.M.V. Bolzani;M. Rebaudengo;M.S. Reorda

  • A diagnostic test pattern generation algorithm

    Unknown

  • Fully automatic test program generation for microprocessor cores

    Unknown

  • GALLO: a genetic algorithm for floorplan area optimization

    M. Rebaudengo;M.S. Reorda

  • An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor

    M. Rebaudengo;M.S. Reorda;M. Violante

Frequent Co-Authors

Maurizio Rebaudengo
Maurizio Rebaudengo Polytechnic University of Turin
Fulvio Corno
Fulvio Corno Polytechnic University of Turin
Massimo Violante
Massimo Violante Polytechnic University of Turin
Zebo Peng
Zebo Peng Linköping University
Luigi Carro
Luigi Carro Federal University of Rio Grande do Sul
Said Hamdioui
Said Hamdioui Delft University of Technology
Patrick Girard
Patrick Girard Montpellier Laboratory of Informatics, Robotics and Microelectronics
Bernd Becker
Bernd Becker University of Freiburg
Alessandro Paccagnella
Alessandro Paccagnella University of Padua
Luciano Lavagno
Luciano Lavagno Polytechnic University of Turin

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