H-Index & Metrics Best Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Computer Science D-index 35 Citations 5,393 195 World Ranking 5759 National Ranking 37

Research.com Recognitions

Awards & Achievements

2004 - IEEE Fellow For contributions to design and test of array structures.

Overview

What is he best known for?

The fields of study he is best known for:

  • Central processing unit
  • Electrical engineering
  • Algorithm

Cheng-Wen Wu spends much of his time researching Embedded system, Computer hardware, Built-in self-test, Algorithm and Redundancy. His Embedded system research includes themes of Overhead, Throughput, Fault, CMOS and Testability. The study incorporates disciplines such as Field-programmable gate array and Logic synthesis in addition to Fault.

His Built-in self-test research is multidisciplinary, incorporating elements of Burn-in, Control theory, System on a chip and Static random-access memory. His studies in Algorithm integrate themes in fields like Automatic testing, Memory array and Logic testing. His Redundancy study combines topics in areas such as Spare part, Error detection and correction, Semiconductor memory and Read-write memory.

His most cited work include:

  • VLSI Test Principles and Architectures: Design for Testability (304 citations)
  • Built-in redundancy analysis for memory yield improvement (165 citations)
  • On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification (134 citations)

What are the main themes of his work throughout his whole career to date?

Cheng-Wen Wu focuses on Embedded system, Built-in self-test, Electronic engineering, Computer hardware and Parallel computing. His Embedded system research incorporates themes from Design for testing, Fault, Chip and Static random-access memory. Cheng-Wen Wu interconnects Overhead, Read-write memory, Very-large-scale integration, Redundancy and Scheme in the investigation of issues within Built-in self-test.

Cheng-Wen Wu has researched Redundancy in several fields, including Dram, Spare part and Semiconductor memory. His research investigates the link between Electronic engineering and topics such as Three-dimensional integrated circuit that cross with problems in Interconnection. His research in Parallel computing focuses on subjects like Algorithm, which are connected to Arithmetic.

He most often published in these fields:

  • Embedded system (28.49%)
  • Built-in self-test (20.00%)
  • Electronic engineering (18.08%)

What were the highlights of his more recent work (between 2011-2020)?

  • Electronic engineering (18.08%)
  • Embedded system (28.49%)
  • Three-dimensional integrated circuit (4.93%)

In recent papers he was focusing on the following fields of study:

Cheng-Wen Wu mainly investigates Electronic engineering, Embedded system, Three-dimensional integrated circuit, Dram and Reliability engineering. The Electronic engineering study combines topics in areas such as Fault, Electronic circuit and Chip. His Chip research includes elements of Integrated circuit layout, Computer hardware and Boundary scan.

His study looks at the intersection of Embedded system and topics like Spare part with Fuse. His study in Three-dimensional integrated circuit is interdisciplinary in nature, drawing from both NAND gate, Through-silicon via, Design for testing and Interconnection. His Redundancy study incorporates themes from System on a chip and Parallel computing.

Between 2011 and 2020, his most popular works were:

  • RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme (90 citations)
  • 3D-IC interconnect test, diagnosis, and repair (31 citations)
  • In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis (25 citations)

In his most recent research, the most cited papers focused on:

  • Central processing unit
  • Electrical engineering
  • Integrated circuit

Redundancy, Three-dimensional integrated circuit, Embedded system, Reliability engineering and Built-in self-test are his primary areas of study. Cheng-Wen Wu has included themes like Parallel computing, Through-silicon via, Maintenance engineering, System on a chip and Error detection and correction in his Redundancy study. His Three-dimensional integrated circuit research integrates issues from Design for testing, Physical design and Electronic engineering.

His Electronic engineering research is multidisciplinary, incorporating perspectives in Electronic circuit, Random access memory and Shmoo plot. His Embedded system research is multidisciplinary, relying on both Dram and Spare part. While working on this project, Cheng-Wen Wu studies both Built-in self-test and Stacking.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

VLSI Test Principles and Architectures: Design for Testability

Laung-Terng Wang;Cheng-Wen Wu;Xiaoqing Wen.
(2006)

823 Citations

Built-in redundancy analysis for memory yield improvement

Chih-Tsun Huang;Chi-Feng Wu;Jin-Fu Li;Cheng-Wen Wu.
IEEE Transactions on Reliability (2003)

227 Citations

On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification

Po-Yuan Chen;Cheng-Wen Wu;Ding-Ming Kwai.
asian test symposium (2009)

176 Citations

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Laung-Terng Wang;Cheng-Wen Wu;Xiaoqing Wen.
(2006)

163 Citations

A programmable BIST core for embedded DRAM

Chih-Tsun Huang;Jing-Reng Huang;Chi-Feng Wu;Cheng-Wen Wu.
IEEE Design & Test of Computers (1999)

161 Citations

On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding

Po-Yuan Chen;Cheng-Wen Wu;Ding-Ming Kwai.
vlsi test symposium (2010)

152 Citations

A built-in self-repair design for RAMs with 2-D redundancy

Jin-Fu Li;J.-C. Yeh;Rei-Fu Huang;Cheng-Wen Wu.
IEEE Transactions on Very Large Scale Integration Systems (2005)

133 Citations

Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

Shyue-Kung Lu;Yu-Chen Tsai;C.-H. Hsu;Kuo-Hua Wang.
IEEE Transactions on Very Large Scale Integration Systems (2006)

128 Citations

A high-throughput low-cost AES processor

Chih-Pin Su;Tsung-Fu Lin;Chih-Tsiun Huang;Cheng-Wen Wu.
IEEE Communications Magazine (2003)

128 Citations

RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme

Ching Yi Chen;Hsiu Chuan Shih;Cheng Wen Wu;Chih He Lin.
IEEE Transactions on Computers (2015)

120 Citations

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