H-Index & Metrics Top Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Computer Science H-index 55 Citations 9,989 202 World Ranking 2109 National Ranking 95
Electronics and Electrical Engineering H-index 53 Citations 8,235 213 World Ranking 923 National Ranking 30

Research.com Recognitions

Awards & Achievements

2012 - IEEE Fellow For contributions to digital VLSI circuit testing and test compression

Overview

What is he best known for?

The fields of study he is best known for:

  • Algorithm
  • Integrated circuit
  • Electrical engineering

Janusz Rajski spends much of his time researching Built-in self-test, Algorithm, Automatic test pattern generation, Electronic engineering and Fault coverage. The various areas that Janusz Rajski examines in his Built-in self-test study include Design for testing, Overhead, Shift register, Interconnection and Boundary scan. His Algorithm research includes elements of Polynomial and Scan chain, Integrated circuit.

His biological study focuses on Test compression. He has researched Electronic engineering in several fields, including Test vector, Electronic circuit, System on a chip and Electronics. In his work, Fault indicator, Divide and conquer algorithms and CMOS is strongly intertwined with Stuck-at fault, which is a subfield of Fault coverage.

His most cited work include:

  • Embedded deterministic test (459 citations)
  • Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers (402 citations)
  • Embedded deterministic test for low cost manufacturing test (388 citations)

What are the main themes of his work throughout his whole career to date?

His primary areas of investigation include Automatic test pattern generation, Algorithm, Built-in self-test, Electronic engineering and Test compression. His Automatic test pattern generation research includes themes of Design for testing, Reliability engineering, Computer engineering and Fault coverage. Janusz Rajski combines subjects such as Polynomial, Encoding and Benchmark with his study of Algorithm.

The Built-in self-test study combines topics in areas such as Overhead, Adder and Shift register. His Electronic engineering research incorporates themes from Phase, Electronic circuit, Pseudorandom number generator and Low-power electronics. His Test compression research focuses on subjects like Scan chain, which are linked to Computer hardware, Boundary scan and Test response.

He most often published in these fields:

  • Automatic test pattern generation (35.63%)
  • Algorithm (28.74%)
  • Built-in self-test (23.56%)

What were the highlights of his more recent work (between 2013-2021)?

  • Automatic test pattern generation (35.63%)
  • Test compression (22.13%)
  • Code coverage (7.76%)

In recent papers he was focusing on the following fields of study:

Janusz Rajski mainly investigates Automatic test pattern generation, Test compression, Code coverage, Algorithm and Computer hardware. In his works, Janusz Rajski undertakes multidisciplinary study on Automatic test pattern generation and Test data. His Test compression study which covers Scan chain that intersects with Electronic engineering.

His Algorithm research includes themes of Fault and Benchmark. His Computer hardware research is multidisciplinary, relying on both Electronic circuit and Network packet. His Fault coverage study deals with Built-in self-test intersecting with System on a chip and Computer engineering.

Between 2013 and 2021, his most popular works were:

  • Cell-Aware Test (81 citations)
  • Embedded Deterministic Test Points (21 citations)
  • Trimodal Scan-Based Test Paradigm (16 citations)

In his most recent research, the most cited papers focused on:

  • Algorithm
  • Integrated circuit
  • Electrical engineering

Janusz Rajski focuses on Automatic test pattern generation, Fault coverage, Test compression, Built-in self-test and Algorithm. Janusz Rajski combines subjects such as Electronic engineering, Logic gate and Fault model with his study of Automatic test pattern generation. His Fault coverage research integrates issues from Design for testing, Pseudorandom number generator and Code coverage.

Janusz Rajski usually deals with Design for testing and limits it to topics linked to Testability and Integrated circuit design and Integrated circuit. In his study, which falls under the umbrella issue of Test compression, Digital electronics is strongly linked to Real-time computing. His Algorithm study incorporates themes from Fault and Observability.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Top Publications

Embedded deterministic test

J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2004)

583 Citations

Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

S. Hellebrand;J. Rajski;S. Tarnick;S. Venkataraman.
IEEE Transactions on Computers (1995)

569 Citations

Embedded deterministic test for low cost manufacturing test

J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee.
international test conference (2002)

456 Citations

Logic BIST for large industrial designs: real issues and case studies

G. Hetherington;T. Fryars;N. Tamarapalli;M. Kassab.
international test conference (1999)

404 Citations

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers

Sybille Hellebrand;Steffen Tarnick;Bernard Courtois;Janusz Rajski.
international test conference (1992)

335 Citations

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

S. Remersaro;X. Lin;Z. Zhang;S.M. Reddy.
international test conference (2006)

289 Citations

Arithmetic built-in self-test of multiple scan-based integrated circuits

Janusz Rajski;Jerzy Tyszer.
(2004)

218 Citations

Testing and diagnosis of interconnects using boundary scan architecture

A. Hassan;J. Rajski;V.K. Agarwal.
international test conference (1988)

216 Citations

Arithmetic Built-In Self-Test for Embedded Systems

Janusz Rajski;Jerzy Tyszer.
(1997)

213 Citations

Impact of multiple-detect test patterns on product quality

B. Benware;C. Schuermyer;N. Tamarapalli;Kun-Han Tsai.
international test conference (2003)

211 Citations

Profile was last updated on December 6th, 2021.
Research.com Ranking is based on data retrieved from the Microsoft Academic Graph (MAG).
The ranking h-index is inferred from publications deemed to belong to the considered discipline.

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