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Janusz Rajski

Janusz Rajski

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Computer Science
Germany
2025

D-Index & Metrics

Computer Science

D-Index
67
Citations
14987
World Ranking
2227
National Ranking
93

Electronics and Electrical Engineering

D-Index
64
Citations
14423
World Ranking
1313
National Ranking
38

Research.com Recognitions

  • 2025 - Research.com Computer Science in Germany Leader Award
  • 2023 - Research.com Computer Science in Germany Leader Award
  • 2022 - Research.com Computer Science in Germany Leader Award
  • 2012 - IEEE Fellow For contributions to digital VLSI circuit testing and test compression

Overview

Janusz Rajski is affiliated with Siemens in Germany. Their research primarily centers on engineering and computer science, with a notable focus on electrical and electronic engineering and hardware and architecture. Additional subfields include computer vision and pattern recognition, control and systems engineering, and artificial intelligence.

The scientist's work extensively covers the following topics:

  • VLSI and Analog Circuit Testing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Radiation Effects in Electronics
  • Chaos-based Image/Signal Encryption
  • VLSI and FPGA Design Techniques
  • Engineering and Test Systems

Rajski has published in several frequently appearing venues, including:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Design and Test
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • Journal of Electronic Testing

Some of the recent papers authored or co-authored by Janusz Rajski include:

  • "Defect-Oriented Test: Effectiveness in High Volume Manufacturing," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "A Lightweight True Random Number Generator for Root of Trust Applications," 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "The Future of Design for Test and Silicon Lifecycle Management," 2023, IEEE Design and Test
  • "Time and Area Optimized Testing of Automotive ICs," 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "LBIST for Automotive ICs With Enhanced Test Generation," 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Frequent collaborators in their research include Jerzy Tyszer, Bartosz Włodarczak, Nilanjan Mukherjee, Maciej Trawka, and Grzegorz Mrugalski.

Janusz Rajski was recognized as an IEEE Fellow in 2012 for contributions to digital VLSI circuit testing and test compression.

Best Publications

  • Embedded deterministic test

    J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee

  • Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

    S. Hellebrand;J. Rajski;S. Tarnick;S. Venkataraman

  • Embedded deterministic test for low cost manufacturing test

    J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee

  • Logic BIST for large industrial designs: real issues and case studies

    G. Hetherington;T. Fryars;N. Tamarapalli;M. Kassab

  • Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers

    Sybille Hellebrand;Steffen Tarnick;Bernard Courtois;Janusz Rajski

  • Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

    Santiago Remersaro;Xijiang Lin;Zhuo Zhang;Sudhakar Reddy

  • Testing and diagnosis of interconnects using boundary scan architecture

    A. Hassan;J. Rajski;V.K. Agarwal

  • Arithmetic built-in self-test of multiple scan-based integrated circuits

    Janusz Rajski;Jerzy Tyszer

  • Arithmetic Built-In Self-Test for Embedded Systems

    Janusz Rajski;Jerzy Tyszer

  • Impact of multiple-detect test patterns on product quality

    B. Benware;C. Schuermyer;N. Tamarapalli;Kun-Han Tsai

  • High-frequency, at-speed scan testing

    Xijiiang Lin;R. Press;J. Rajski;P. Reuter

  • Test pattern compression for an integrated circuit test environment

    Janusz Rajski;Mark Kassab;Nilanjan Mukherjee;Jerzy Tyszer

  • Cell-Aware Test

    Friedrich Hapke;Wilfried Redemund;Andreas Glowatz;Janusz Rajski

  • Decompressor/PRPG for applying pseudo-random and deterministic test patterns

    Janusz Rajski;Jerzy Tyszer;Mark Kassab;Nilanjan Mukherjee

  • A method of fault analysis for test generation and fault diagnosis

    H. Cox;J. Rajski

  • Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

    Xijiang Lin;Kun-Han Tsai;Chen Wang;M. Kassab

  • Fault dictionaries for integrated circuit yield and quality analysis methods and systems

    Janusz Rajski;Gang Chen;Martin Keim;Nagesh Tamarapalli

  • Constructive multi-phase test point insertion for scan-based BIST

    N. Tamarapalli;J. Rajski

  • Convolutional compaction of test responses

    J. Rajski;J. Tyszer;Chen Wang;S.M. Reddy

  • GENERATION OF VECTOR PATTTERNS THROUGH RESEEDING OF MUETIPLE-POLYNOMIAL LINEAR FEEDBACK SHIFT REGIST

    S. Hellebrand;S. Tarnick;J. Rajski;B. Courtois

Frequent Co-Authors

Jerzy Tyszer
Jerzy Tyszer Poznań University of Technology
Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Wu-Tung Cheng
Wu-Tung Cheng Mentor Graphics
Irith Pomeranz
Irith Pomeranz Purdue University West Lafayette
Malgorzata Marek-Sadowska
Malgorzata Marek-Sadowska University of California, Santa Barbara
Wojciech Maly
Wojciech Maly Carnegie Mellon University
Bashir M. Al-Hashimi
Bashir M. Al-Hashimi King's College London
Edward J. McCluskey
Edward J. McCluskey Stanford University
Sujit Dey
Sujit Dey University of California, San Diego
Miodrag Potkonjak
Miodrag Potkonjak University of California, Los Angeles

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