His main research concerns Electronic engineering, Very-large-scale integration, CMOS, Current and Stuck-at fault. The various areas that Wojciech Maly examines in his Electronic engineering study include Electronic circuit, Electrical engineering, Integrated circuit, Reliability engineering and Manufacturing process. His Reliability engineering study incorporates themes from Characterization, Fault analysis and Fault list.
His Very-large-scale integration study combines topics from a wide range of disciplines, such as Maximization, Process control, Computer Aided Design and Lithography. Wojciech Maly combines subjects such as Iddq testing, Die, Block diagram and Automatic testing with his study of Current. Wojciech Maly has researched Stuck-at fault in several fields, including Fault model, Automatic test pattern generation and Mixed-signal integrated circuit.
Wojciech Maly mainly investigates Electronic engineering, Very-large-scale integration, Reliability engineering, CMOS and Integrated circuit. His research in Electronic engineering intersects with topics in Electronic circuit, Die, Critical area, Transistor and Integrated circuit layout. His Very-large-scale integration research incorporates themes from Yield, Physical design, Manufacturing engineering and Computer architecture.
The concepts of his Reliability engineering study are interwoven with issues in Test, Computer-aided manufacturing, Static random-access memory, Fault and Manufacturing process. His study looks at the relationship between CMOS and fields such as Current, as well as how they intersect with chemical problems. His Integrated circuit research is multidisciplinary, incorporating elements of Algorithm and Computer Aided Design.
Wojciech Maly focuses on Transistor, Field-effect transistor, Electronic engineering, CMOS and Electrical engineering. The Transistor study combines topics in areas such as Electronic circuit, Integrated circuit layout, Logic gate and Design for manufacturability. In the subject of general Electronic engineering, his work in Vlsi systems and Very-large-scale integration is often linked to Page layout, thereby combining diverse domains of study.
His CMOS research integrates issues from Integrated circuit design, Transistor count and Chip. His study in the fields of Integrated circuit and NMOS logic under the domain of Electrical engineering overlaps with other disciplines such as Silicon on insulator and Thermal. His Integrated circuit study combines topics in areas such as Terminal, Reliability engineering and Logic level.
Wojciech Maly mainly focuses on Transistor, Electronic engineering, Integrated circuit layout, Optoelectronics and Field-effect transistor. His work in Transistor addresses issues such as Logic gate, which are connected to fields such as MOSFET. He specializes in Electronic engineering, namely CMOS.
In general CMOS study, his work on Full custom often relates to the realm of NAND logic, thereby connecting several areas of interest. As a member of one scientific family, Wojciech Maly mostly works in the field of Integrated circuit layout, focusing on IC layout editor and, on occasion, Place and route, Design layout record, Electronic circuit, Routing and Design for manufacturability. His research in Optoelectronics tackles topics such as Sram cell which are related to areas like Slit, Double gate, Transconductance, Memory cell and Robustness.
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Inductive Fault Analysis of MOS Integrated Circuits
John P. Shen;W. Maly;F. Joel Ferguson.
IEEE Design & Test of Computers (1985)
Inductive Fault Analysis of MOS Integrated Circuits
John P. Shen;W. Maly;F. Joel Ferguson.
IEEE Design & Test of Computers (1985)
Realistic Fault Modeling for VLSI Testing
W. Maly.
design automation conference (1987)
Realistic Fault Modeling for VLSI Testing
W. Maly.
design automation conference (1987)
CMOS bridging fault detection
T.M. Storey;W. Maly.
international test conference (1990)
CMOS bridging fault detection
T.M. Storey;W. Maly.
international test conference (1990)
Test generation for current testing (CMOS ICs)
P. Nigh;W. Maly.
IEEE Design & Test of Computers (1990)
Test generation for current testing (CMOS ICs)
P. Nigh;W. Maly.
IEEE Design & Test of Computers (1990)
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
W. Maly.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1985)
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
W. Maly.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1985)
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