World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
30
Citations
3632
World Ranking
6819
National Ranking
144

Overview

Michel Renovell is affiliated with the Montpellier Laboratory of Informatics, Robotics and Microelectronics in France. Their research spans multiple fields, primarily within engineering and medicine, with a focus on electrical and electronic engineering, physiology, and surgery. Renovell's work spans several subfields including hardware and architecture, as well as surfaces, coatings, and films.

The scientist's main research topics include integrated circuits and semiconductor failure analysis, body composition measurement techniques, semiconductor materials and devices, electrical and bioimpedance tomography, hemodynamic monitoring and therapy, advancements in semiconductor devices and circuit design, and VLSI and analog circuit testing.

Renovell has contributed to a range of publications, notable recent papers include:

  • "Multilinear Regression Analysis between Local Bioimpedance Spectroscopy and Fish Morphological Parameters," 2023, published in Fishes
  • "B-open Defect: A Novel Defect Model in FinFET Technology," 2022, published in ACM Journal on Emerging Technologies in Computing Systems
  • "Study Differentiating Fish Oocyte Developmental Stages Using Bioimpedance Spectroscopy," 2021, published in Aquaculture
  • "Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology," 2024, published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers," forthcoming 2025, published in Journal of Electronic Testing

Frequent co-authors with whom Renovell has collaborated include Freddy Forero, Victor Champac, Vincent Kerzérho, F. Azaïs, and Serge Bernard.

The scientist's work has appeared in various publication venues, encompassing:

  • Fishes
  • ACM Journal on Emerging Technologies in Computing Systems
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Aquaculture
  • Journal of Electronic Testing

Michel Renovell's research integrates multiple aspects of engineering and medicine, reflecting interdisciplinary interests at the interface of electrical engineering and biological applications.

Best Publications

  • Testing the interconnect of RAM-based FPGAs

    M. Renovell;J.M. Portal;J. Figueras;Y. Zorian

  • Scan design and secure chip [secure IC testing]

    D. Hely;M.-L. Flottes;F. Bancel;B. Rouzeyre

  • Scan Design and Secure Chip

    David Hely;Marie-Lise Flottes;Frederic Bancel;Bruno Rouzeyre

  • Test of RAM-based FPGA: methodology and application to the interconnect

    M. Renovell;J. Figueras;Y. Zorian

  • Simulating Resistive-Bridging and Stuck-At Faults

    Piet Engelke;I. Polian;M. Renovell;B. Becker

  • The concept of resistance interval: a new parametric model for realistic resistive bridging fault

    M. Renovell;P. Huc;Y. Bertrand

  • Towards an ADC BIST scheme using the histogram test technique

    F. Azais;S. Bernard;Y. Betrand;M. Renovell

  • Implementation of a linear histogram BIST for ADCs

    F. Azais;S. Bernard;Y. Bertrand;M. Renovell

  • A low-cost adaptive ramp generator for analog BIST applications

    F. Azais;S. Bernard;Y. Bertrand;X. Michel

  • Hardware resource minimization for histogram-based ADC BIST

    M. Renovell;F. Azais;S. Bernard;Y. Bertrand

  • Electrical analysis and modeling of floating-gate fault

    Unknown

  • A high accuracy triangle-wave signal generator for on-chip ADC testing

    S. Bernard;F. Azais;Y. Bertrand;M. Renovell

  • CMOS bridging fault modeling

    M. Renovell;P. Huc;Y. Bertrand

  • A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

    A. Czutro;N. Houarche;P. Engelke;I. Polian

  • Testing for floating gates defects in CMOS circuits

    S. Rafiq;A. Ivanov;S. Tabatabaei;M. Renovell

  • Topology dependence of floating gate faults in MOS integrated circuits

    Unknown

  • IS-FPGA : a new symmetric FPGA architecture with implicit scan

    M. Renovell;P. Faure;J.M. Portal;J. Figueras

  • SRAM-based FPGA's: testing the LUT/RAM modules

    M. Renovell;J.M. Portal;J. Figueras;Y. Zorian

  • Resistive Bridge fault model evolution from conventional to ultra deep submicron

    I. Polian;P. Engelke;B. Becker;S. Kundu

  • An all-digital DFT scheme for testing catastrophic faults in PLLs

    F. Azais;Y. Bertrand;M. Renovell;A. Ivanov

  • A multi-configuration strategy for an application dependent testing of FPGAs

    M.B. Tahoori;E.J. McCluskey;M. Renovell;P. Faure

  • RAM-based FPGA's: a test approach for the configurable logic

    M. Renovell;J. M. Portal;J. Figueras;Y. Zorian

  • Different experiments in test generation for XILINX FPGAs

    Unknown

  • Making predictive analog/RF alternate test strategy independent of training set size

    Haithem Ayari;Florence Azais;Serge Bernard;Mariane Comte

Frequent Co-Authors

Andre Ivanov
Andre Ivanov University of British Columbia
Luigi Carro
Luigi Carro Federal University of Rio Grande do Sul
Sandip Kundu
Sandip Kundu University of Massachusetts Amherst
Krishnendu Chakrabarty
Krishnendu Chakrabarty Arizona State University
Jerzy Tyszer
Jerzy Tyszer Poznań University of Technology
Abhijit Chatterjee
Abhijit Chatterjee Georgia Institute of Technology
Jacob A. Abraham
Jacob A. Abraham The University of Texas at Austin

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