World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
42
Citations
6591
World Ranking
4145
National Ranking
8

Research.com Recognitions

  • 2013 - IEEE Fellow For contributions to digital VLSI circuit testing and test compression

Overview

Jerzy Tyszer is affiliated with the Poznań University of Technology in Poland. Their research contributions span across fields centered on computer science and engineering, with a strong focus on electrical and electronic engineering, and hardware and architecture.

The main fields of study covered by their work include:

  • Computer Science
  • Engineering

Subfields of interest involve:

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Control and Systems Engineering
  • Artificial Intelligence

Tyszer's research topics primarily address:

  • VLSI and Analog Circuit Testing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Radiation Effects in Electronics
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Chaos-based Image/Signal Encryption
  • Engineering and Test Systems
  • Advanced Steganography and Watermarking Techniques

The scientist has published extensively in IEEE journals, with frequent contributions to these venues:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • IEEE Design and Test
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • Journal of Electronic Testing

Recent publications include:

  • "A Lightweight True Random Number Generator for Root of Trust Applications", 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "The Future of Design for Test and Silicon Lifecycle Management", 2023, IEEE Design and Test
  • "Time and Area Optimized Testing of Automotive ICs", 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "LBIST for Automotive ICs With Enhanced Test Generation", 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan", 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Frequent co-authors collaborating with Tyszer include:

  • Janusz Rajski
  • Bartosz Włodarczak
  • Maciej Trawka
  • Nilanjan Mukherjee
  • Grzegorz Mrugalski

Tyszer received the IEEE Fellow award in 2013 for contributions to digital VLSI circuit testing and test compression.

Best Publications

  • Embedded deterministic test

    J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee

  • Embedded deterministic test for low cost manufacturing test

    J. Rajski;J. Tyszer;M. Kassab;N. Mukherjee

  • Arithmetic built-in self-test of multiple scan-based integrated circuits

    Janusz Rajski;Jerzy Tyszer

  • Arithmetic Built-In Self-Test for Embedded Systems

    Janusz Rajski;Jerzy Tyszer

  • Test pattern compression for an integrated circuit test environment

    Janusz Rajski;Mark Kassab;Nilanjan Mukherjee;Jerzy Tyszer

  • Convolutional compaction of test responses

    J. Rajski;J. Tyszer;Chen Wang;S.M. Reddy

  • Test responses compaction in accumulators with rotate carry adders

    J. Rajski;J. Tyszer

  • Test data decompression for multiple scan designs with boundary scan

    J. Rajski;J. Tyszer;N. Zacharia

  • On-chip comparison and response collection tools and techniques

    Nilanjan Mukherjee;Janusz Rajski;Jerzy Tyszer

  • Parallel decompressor and related methods and apparatuses

    Janusz Rajski;Jerzy Tyszer

  • Decompression of test data using variable-length seed LFSRs

    N. Zacharia;J. Rajski;J. Tyszer

  • Ring generators - new devices for embedded test applications

    G. Mrugalski;J. Rajski;J. Tyszer

  • Accumulator-based compaction of test responses

    J. Rajski;J. Tyszer

  • Diagnosis of scan cells in BIST environment

    J. Rajski;J. Tyszer

  • Automated synthesis of phase shifters for built-in self-test applications

    J. Rajski;N. Tamarapalli;J. Tyszer

  • Finite memory test response compactors for embedded test applications

    J. Rajski;J. Tyszer;Chen Wang;S.M. Reddy

  • Arithmetic additive generators of pseudo-exhaustive test patterns

    S. Gupta;J. Rajski;J. Tyszer

  • Automated synthesis of large phase shifters for built-in self-test

    J. Rajski;N. Tamarapalli;J. Tyszer

  • Two-dimensional test data decompressor for multiple scan designs

    N. Zacharia;J. Rajski;J. Tyszer;J.A. Waicukauski

  • Low-Power Scan Operation in Test Compression Environment

    D. Czysz;M. Kassab;Xijiang Lin;G. Mrugalski

  • Continuous application and decompression of test patterns to a circuit-under-test

    Janusz Rajski;Jerzy Tyszer;Mark Kassab;Nilanjan Mukherjee

  • Embedded deterministic test for low-cost manufacturing

    J. Rajski;M. Kassab;N. Mukherjee;N. Tamarapalli

  • New test data decompressor for low power applications

    Grzegorz Mrugalski;Janusz Rajski;Dariusz Czysz;Jerzy Tyszer

  • Low Power Scan Shift and Capture in the EDT Environment

    D. Czysz;M. Kassab;X. Lin;G. Mrugalski

Frequent Co-Authors

Janusz Rajski
Janusz Rajski Siemens (Germany)
Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Wu-Tung Cheng
Wu-Tung Cheng Mentor Graphics
Yu Huang
Yu Huang University of California, Los Angeles
Irith Pomeranz
Irith Pomeranz Purdue University West Lafayette
Michel Renovell
Michel Renovell Montpellier Laboratory of Informatics, Robotics and Microelectronics
Krishnendu Chakrabarty
Krishnendu Chakrabarty Arizona State University
Abhijit Chatterjee
Abhijit Chatterjee Georgia Institute of Technology

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