2009 - IEEE Fellow For contributions to data compression and built-in self-test for integrated circuits
Nur A. Touba spends much of her time researching Built-in self-test, Algorithm, Automatic test pattern generation, Parallel computing and Test data. Her research in Built-in self-test focuses on subjects like Real-time computing, which are connected to Probabilistic logic, Core and Integrator. She has researched Algorithm in several fields, including Overhead, Code and Fault detection and isolation.
Her Automatic test pattern generation research is multidisciplinary, relying on both Design for testing and Fault coverage. The Parallel computing study combines topics in areas such as Single event upset and Shift register. Her biological study spans a wide range of topics, including Test compression, Computer hardware and Test vector.
Her main research concerns Algorithm, Automatic test pattern generation, Fault coverage, Built-in self-test and Computer hardware. Her studies deal with areas such as Electronic engineering and Shift register as well as Algorithm. Her Automatic test pattern generation study combines topics from a wide range of disciplines, such as Design for testing, Test set and Parallel computing.
Her research investigates the connection between Built-in self-test and topics such as Testability that intersect with issues in FLOPS. Her research integrates issues of Chip, Automatic test equipment, Embedded system, Test compression and Test data in her study of Computer hardware. Her study explores the link between Test data and topics such as Test vector that cross with problems in Lossless compression.
Nur A. Touba focuses on Algorithm, Decoding methods, Computer hardware, Test compression and Electronic engineering. Her Algorithm research includes elements of Dram and Built-in self-test. Her biological study deals with issues like Fault coverage, which deal with fields such as Overhead, Discrete mathematics and Testability.
Her Test compression study integrates concerns from other disciplines, such as Test data, Scan chain and Shift register. Nur A. Touba interconnects Fault tolerance, Design for testing and Integer programming in the investigation of issues within Electronic engineering. Her work deals with themes such as FIFO, Circuit complexity and Parallel computing, which intersect with Automatic test pattern generation.
Algorithm, Computer hardware, Electronic engineering, Scan chain and Fault coverage are her primary areas of study. Nur A. Touba works mostly in the field of Algorithm, limiting it down to topics relating to Test compression and, in certain cases, Test data, as a part of the same area of interest. Her Computer hardware research is multidisciplinary, incorporating perspectives in Linear programming, Transmission, Sequential logic and Integer programming.
Her Electronic engineering research incorporates elements of Design for testing, Observability and Overhead. Nur A. Touba has included themes like Fault tolerance and Very-large-scale integration in her Design for testing study. Her Fault coverage research integrates issues from Testability, Pseudorandom number generator and Built-in self-test.
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Survey of Test Vector Compression Techniques
IEEE Design & Test of Computers (2006)
Static compaction techniques to control scan vector power dissipation
R. Sankaralingam;R.R. Oruganti;N.A. Touba.
vlsi test symposium (2000)
Scan vector compression/decompression using statistical coding
A. Jas;J. Ghosh-Dastidar;N.A. Touba.
vlsi test symposium (1999)
Test vector decompression via cyclical scan chains and its application to testing core-based designs
A. Jas;N.A. Touba.
international test conference (1998)
An efficient test vector compression scheme using selective Huffman coding
A. Jas;J. Ghosh-Dastidar;Mom-Eng Ng;N.A. Touba.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2003)
Cost-effective approach for reducing soft error failure rate in logic circuits
K. Mohanram;N.A. Touba.
international test conference (2003)
Test vector encoding using partial LFSR reseeding
C.V. Krishna;A. Jas;N.A. Touba.
international test conference (2001)
Altering a pseudo-random bit sequence for scan-based BIST
N.A. Touba;E.J. McCluskey.
international test conference (1996)
Reducing test data volume using LFSR reseeding with seed compression
C.V. Krishna;N.A. Touba.
international test conference (2002)
Logic synthesis of multilevel circuits with concurrent error detection
N.A. Touba;E.J. McCluskey;E.J. McCluskey.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1997)
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