World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
31
Citations
4314
World Ranking
13627
National Ranking
5438

Overview

Alex Orailoglu is affiliated with the University of California, San Diego in the United States. Their research spans fields primarily in Computer Science and Engineering, with a particular focus on subfields such as Electrical and Electronic Engineering, Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture, and Cellular and Molecular Neuroscience.

The scientist's work covers key topics including Advanced Neural Network Applications, Adversarial Robustness in Machine Learning, Physical Unclonable Functions (PUFs) and Hardware Security, Radiation Effects in Electronics, Integrated Circuits and Semiconductor Failure Analysis, Neuroscience and Neural Engineering, and Semiconductor materials and devices.

Frequent co-authors of Alex Orailoglu include Elbruz Ozen, Marc Reichenbach, Matthias Jung, Leon Li, and Chris Nigh.

Some of the venues where their research has been published multiple times are:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Design and Test
  • International Journal of Parallel Programming
  • ACM Transactions on Embedded Computing Systems
  • 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Recent research papers authored or co-authored by Alex Orailoglu include:

  • Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking, 2020, arXiv (Cornell University)
  • SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks, 2021, ACM Transactions on Embedded Computing Systems
  • JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption, 2022, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
  • Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums, 2020, Journal of Electronic Testing

Alex Orailoglu has contributed to several book publications with Springer Science+Business Media. A notable example is Embedded Computer Systems: Architectures, Modeling, and Simulation, published multiple times from 2020 to 2022.

Best Publications

  • Test volume and application time reduction through scan chain concealment

    Ismet Bayraktaroglu;Alex Orailoglu

  • Flow Graph Representation

    Alex Orailoglu;Daniel D. Gajski

  • Reducing Test Application Time Through Test Data Mutation Encoding

    S. Reda;A. Orailoglu

  • Architectures for silicon nanoelectronics and beyond

    R.I. Bahar;C. Lau;D. Hammerstrom;D. Marculescu

  • Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

    I. Bayraktaroglu;A. Orailoglu

  • Automatic synthesis of self-recovering VLSI systems

    A. Orailoglu;R. Karri

  • Circularscan: a scan architecture for test cost reduction

    Baris Arslan;Alex Orailoglu

  • Test application time and volume compression through seed overlapping

    Wenjing Rao;Ismet Bayraktaroglu;Alex Orailoglu

  • Concurrent application of compaction and compression for test time and data volume reduction in scan designs

    I. Bayraktaroglu;A. Orailoglu

  • Microarchitectural synthesis of performance-constrained, low-power VLSI designs

    Laurence Goodby;Alex Orailoğlu;Paul M. Chau

  • Microarchitectural synthesis of performance-constrained, low-power VLSI designs

    L. Goodby;A. Orailoglu;P.M. Chau

  • Low-power instruction bus encoding for embedded processors

    P. Petrov;A. Orailoglu

  • Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

    Elbruz Ozen;Alex Orailoglu

  • A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise and delay on processor buses

    Raid Ayoub;Alex Orailoglu

  • Microarchitectural Synthesis of VLSI Designs with High Test Concurrency

    Ian G. Harris;Alex Orailoglu

  • Test cost minimization through adaptive test development

    Mingjing Chen;A. Orailoglu

  • A novel scan architecture for power-efficient, rapid test

    Ozgur Sinanoglu;Alex Orailoglu

  • Piercing Logic Locking Keys through Redundancy Identification

    Leon Li;Alex Orailoglu

  • Scan power reduction through test data transition frequency analysis

    O. Sinanoglu;I. Bayraktaroglu;A. Orailoglu

  • Modeling scan chain modifications for scan-in test power minimization

    O. Sinanoglu;A. Orailoglu

  • Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures

    A. Orailoglu;R. Karri

  • RTL Test Justification and Propagation Analysis for Modular Designs

    Yiorgos Makris;Alex Orailoǧlu

Frequent Co-Authors

Ramesh Karri
Ramesh Karri New York University
Ozgur Sinanoglu
Ozgur Sinanoglu New York University Abu Dhabi
Yiorgos Makris
Yiorgos Makris The University of Texas at Dallas
Chun Jason Xue
Chun Jason Xue Mohamed bin Zayed University of Artificial Intelligence
Luigi Carro
Luigi Carro Federal University of Rio Grande do Sul
Sherief Reda
Sherief Reda Brown University
Tongquan Wei
Tongquan Wei East China Normal University
Massoud Pedram
Massoud Pedram University of Southern California
Wojciech Maly
Wojciech Maly Carnegie Mellon University
Swarup Bhunia
Swarup Bhunia University of Florida

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