World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
44
Citations
7694
World Ranking
7600
National Ranking
3295

Electronics and Electrical Engineering

D-Index
42
Citations
7253
World Ranking
4107
National Ranking
1468

Overview

Kewal K. Saluja is affiliated with the University of Wisconsin-Madison in the United States. Their research spans multiple fields within Computer Science, Engineering, and Medicine, with a focus on various subfields such as Electrical and Electronic Engineering, Hardware and Architecture, Computational Theory and Mathematics, Artificial Intelligence, and Oncology.

The main topics of Saluja's work include:

  • VLSI and Analog Circuit Testing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Radiation Effects in Electronics
  • VLSI and FPGA Design Techniques
  • Matrix Theory and Algorithms
  • Quantum Computing Algorithms and Architecture
  • Parallel Computing and Optimization Techniques

Saluja has collaborated frequently with several researchers, including Yoshinobu Higami, Tsutomu Inamoto, Senling Wang, Hiroshi Takahashi, and Takaya Yamauchi. These collaborations have contributed to research outputs across engineering and computing disciplines.

Publications by Saluja have appeared in various venues such as:

  • 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
  • 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
  • Journal of Electronic Testing
  • IIUM Engineering Journal

Recent papers authored or co-authored by Saluja include:

  • "Machine Learning Based Fault Diagnosis for Stuck-at Faults and Bridging Faults," 2022, presented at the 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
  • "Compaction of Fault Dictionary without Degrading Diagnosis Ability," 2021, presented at the 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
  • "Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method," 2021, published in the Journal of Electronic Testing
  • "Boundary-Aware Saliency-Based Level Set with Momentum Contrast Metaformer for Skin Cancer Segmentation and Classification," 2025, published in IIUM Engineering Journal

The research output by Saluja reflects work that intersects fault diagnosis in integrated circuits, algorithm development, and applications in medical imaging and cancer classification. This indicates an interdisciplinary approach linking engineering principles with computational techniques.

Best Publications

  • Sensor deployment strategy for target detection

    Thomas Clouqueur;Veradej Phipatanasuphorn;Parameswaran Ramanathan;Kewal K. Saluja

  • A tutorial on built-in self-test. I. Principles

    V.D. Agrawal;C.R. Kime;K.K. Saluja

  • Scheduling tests for VLSI systems under power constraints

    R.M. Chou;K.K. Saluja;V.D. Agrawal

  • Fault tolerance in collaborative sensor networks for target detection

    T. Clouqueur;K.K. Saluja;P. Ramanathan

  • A tutorial on built-in self-test. 2. Applications

    V.D. Agrawal;C.R. Kime;K.K. Saluja

  • On low-capture-power test generation for scan testing

    Xiaoqing Wen;Y. Yamashita;S. Kajihara;Laung-Terng Wang

  • Sensor deployment strategy for detection of targets traversing a region

    Thomas Clouqueur;Veradej Phipatanasuphorn;Parameswaran Ramanathan;Kewal K. Saluja

  • Low-capture-power test generation for scan-based at-speed testing

    Xiaoqing Wen;Y. Yamashita;S. Morishima;S. Kajihara

  • Testing Computer Hardware through Data Compression in Space and Time.

    Kewal K. Saluja;Mark G. Karpovsky

  • Test scheduling and control for VLSI built-in self-test

    G.L. Craig;C.R. Kine;K.K. Saluja

  • A data compression technique for built-in self-test

    S. M. Reddy;K. K. Saluja;M. G. Karpovsky

  • Fault Detecting Test Sets for Reed-Muller Canonic Networks

    K.K. Saluja;S.M. Reddy

  • An efficient algorithm for sequential circuit test generation

    T.P. Kelsey;K.K. Saluja;S.Y. Lee

  • A concurrent testing technique for digital circuits

    K.K. Saluja;R. Sharma;C.R. Kime

  • A new ATPG method for efficient capture power reduction during scan testing

    Xiaoqing Wen;S. Kajihara;K. Miyase;T. Suzuki

  • A study of time-redundant fault tolerance techniques for high-performance pipelined computers

    G.S. Sohi;M. Franklin;K.K. Saluja

  • Power constraint scheduling of tests

    R.M. Chou;K.K. Saluja;V.D. Agrawal

  • Fast test generation for sequential circuits

    T.P. Kelsey;K.K. Saluja

  • Incorporating testability considerations in high-level synthesis

    A. Mujumdar;K. Saluja;R. Jain

  • Test application time reduction for sequential circuits with scan

    Soo Young Lee;K.K. Saluja

Frequent Co-Authors

Parameswaran Ramanathan
Parameswaran Ramanathan University of Wisconsin–Madison
Seiji Kajihara
Seiji Kajihara Kyushu Institute of Technology
Xiaoqing Wen
Xiaoqing Wen Kyushu Institute of Technology
Michael J. Franklin
Michael J. Franklin University of Chicago
Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Vishwani D. Agrawal
Vishwani D. Agrawal Auburn University
Shambhu Upadhyaya
Shambhu Upadhyaya University at Buffalo, State University of New York
Mark G. Karpovsky
Mark G. Karpovsky Boston University
Mikko H. Lipasti
Mikko H. Lipasti University of Wisconsin–Madison
Brian D. O. Anderson
Brian D. O. Anderson Australian National University

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