H-Index & Metrics Best Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Computer Science D-index 32 Citations 5,210 176 World Ranking 7026 National Ranking 3323

Overview

What is he best known for?

The fields of study he is best known for:

  • Operating system
  • Algorithm
  • Central processing unit

His primary areas of study are Automatic test pattern generation, Algorithm, Built-in self-test, Electronic engineering and Test compression. The various areas that Kewal K. Saluja examines in his Automatic test pattern generation study include Sequential logic, Reduction, Fault coverage and Scan chain. His biological study spans a wide range of topics, including Test vector, Stuck-at fault, Test set and Benchmark.

His research in Built-in self-test intersects with topics in Scheduling and Computer architecture. In his research on the topic of Electronic engineering, Simulation, Low-power electronics, Circuit switching and Reliability is strongly related with Power network design. His work is dedicated to discovering how Fault, State are connected with Fault detection and isolation and other disciplines.

His most cited work include:

  • Sensor deployment strategy for target detection (354 citations)
  • Scheduling tests for VLSI systems under power constraints (285 citations)
  • A tutorial on built-in self-test. I. Principles (252 citations)

What are the main themes of his work throughout his whole career to date?

Algorithm, Automatic test pattern generation, Fault, Electronic engineering and Embedded system are his primary areas of study. His work deals with themes such as Test vector, Fault detection and isolation and Benchmark, which intersect with Algorithm. His Automatic test pattern generation research incorporates themes from Design for testing, Reduction, Fault coverage and Scan chain.

Kewal K. Saluja interconnects Process, Real-time computing and Parallel computing in the investigation of issues within Fault. His work investigates the relationship between Real-time computing and topics such as Software deployment that intersect with problems in Wireless sensor network. Scheduling is closely connected to Integrated circuit in his research, which is encompassed under the umbrella topic of Embedded system.

He most often published in these fields:

  • Algorithm (24.57%)
  • Automatic test pattern generation (22.18%)
  • Fault (20.82%)

What were the highlights of his more recent work (between 2007-2021)?

  • Real-time computing (16.04%)
  • Electronic engineering (20.48%)
  • Embedded system (16.38%)

In recent papers he was focusing on the following fields of study:

The scientist’s investigation covers issues in Real-time computing, Electronic engineering, Embedded system, Logic gate and Fault. The concepts of his Real-time computing study are interwoven with issues in Software deployment, Bridging fault, Wireless sensor network, Fault coverage and Automatic test pattern generation. His Automatic test pattern generation study incorporates themes from Power network design and Computer engineering.

The Electronic engineering study which covers Benchmark that intersects with Fault Simulator and Bridging. He has included themes like Fault tolerance, Redundancy, Chip and Integrated circuit in his Embedded system study. His Logic gate research is under the purview of Algorithm.

Between 2007 and 2021, his most popular works were:

  • Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies (31 citations)
  • Thermal-Aware Test Scheduling Using On-chip Temperature Sensors (29 citations)
  • A Capture-Safe Test Generation Scheme for At-Speed Scan Testing (29 citations)

In his most recent research, the most cited papers focused on:

  • Operating system
  • Central processing unit
  • Algorithm

Kewal K. Saluja focuses on Real-time computing, Electronic engineering, Scheduling, Embedded system and Parallel computing. His work carried out in the field of Real-time computing brings together such families of science as Wireless sensor network, Software deployment and Cost efficiency. His Electronic engineering study integrates concerns from other disciplines, such as Design for testing and Electronic circuit.

The study incorporates disciplines such as Soft error and Algorithm in addition to Electronic circuit. When carried out as part of a general Scheduling research project, his work on Fair-share scheduling is frequently linked to work in Superposition principle, therefore connecting diverse disciplines of study. His research investigates the connection between System on a chip and topics such as Reliability engineering that intersect with issues in Bridging, Computer engineering, Automatic test pattern generation, Stuck-at fault and Fault coverage.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

Sensor deployment strategy for target detection

Thomas Clouqueur;Veradej Phipatanasuphorn;Parameswaran Ramanathan;Kewal K. Saluja.
international workshop on wireless sensor networks and applications (2002)

512 Citations

A tutorial on built-in self-test. I. Principles

V.D. Agrawal;C.R. Kime;K.K. Saluja.
IEEE Design & Test of Computers (1993)

385 Citations

Scheduling tests for VLSI systems under power constraints

R.M. Chou;K.K. Saluja;V.D. Agrawal.
IEEE Transactions on Very Large Scale Integration Systems (1997)

362 Citations

Fault tolerance in collaborative sensor networks for target detection

T. Clouqueur;K.K. Saluja;P. Ramanathan.
IEEE Transactions on Computers (2004)

348 Citations

A tutorial on built-in self-test. 2. Applications

V.D. Agrawal;C.R. Kime;K.K. Saluja.
IEEE Design & Test of Computers (1993)

295 Citations

On low-capture-power test generation for scan testing

Xiaoqing Wen;Y. Yamashita;S. Kajihara;Laung-Terng Wang.
vlsi test symposium (2005)

225 Citations

Sensor deployment strategy for detection of targets traversing a region

Thomas Clouqueur;Veradej Phipatanasuphorn;Parameswaran Ramanathan;Kewal K. Saluja.
Mobile Networks and Applications (2003)

176 Citations

Low-capture-power test generation for scan-based at-speed testing

Xiaoqing Wen;Y. Yamashita;S. Morishima;S. Kajihara.
international test conference (2005)

175 Citations

Testing Computer Hardware through Data Compression in Space and Time.

Kewal K. Saluja;Mark G. Karpovsky.
international test conference (1983)

168 Citations

Test scheduling and control for VLSI built-in self-test

G.L. Craig;C.R. Kine;K.K. Saluja.
IEEE Transactions on Computers (1988)

153 Citations

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