Navab Singh

Navab Singh publication distribution in Electronics and Electrical Engineering in 2026

The chart shows the distribution of publications by all Research.com ranked scientists in the field of Electronics and Electrical Engineering in 2026. The highlighted bar marks where Navab Singh sits on this spectrum.

Navab Singh D-index placement in Electronics and Electrical Engineering in 2026

The chart shows the D-index (discipline H-index) distribution of Electronics and Electrical Engineering scientists ranked by Research.com in 2026. The highlighted bar marks where Navab Singh sits on this spectrum.

Overview

Best Publications

• High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

  N. Singh;A. Agarwal;L.K. Bera;T.Y. Liow

  827
  Citations

• Silicon Nanowire Arrays for Label-Free Detection of DNA

  Zhiqiang Gao;Ajay Agarwal;Alastair D Trigg;Navab Singh

  580
  Citations

• DNA sensing by silicon nanowire: charge layer distance dependence.

  Guo-Jun Zhang;Gang Zhang;Jay Huiyi Chua;Ru-Ern Chee

  354
  Citations

• Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

  R Gandhi;Zhixian Chen;N Singh;K Banerjee

  330
  Citations

• Stacked silicon-germanium nanowire structure and method of forming the same

  Guo Qiang Lo;Lakshmi Kanta Bera;Hoai Son Nguyen;Navab Singh

  288
  Citations

• Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

  B. Yang;K.D. Buddharaju;S.H.G. Teo;N. Singh

  284
  Citations

• Reconfigurable MEMS Fano metasurfaces with multiple-input-output states for logic operations at terahertz frequencies.

  Manukumara Manjappa;Prakash Pitchappa;Navab Singh;Nan Wang

  281
  Citations

• CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$ -mV/decade Subthreshold Swing

  R. Gandhi;Zhixian Chen;N. Singh;K. Banerjee

  254
  Citations

• Active Control of Electromagnetically Induced Transparency Analog in Terahertz MEMS Metamaterial

  Prakash Pitchappa;Prakash Pitchappa;Manukumara Manjappa;Chong Pei Ho;Chong Pei Ho;Chong Pei Ho;Ranjan Singh

  243
  Citations

• Large area patterned magnetic nanostructures

  A O Adeyeye;N Singh;N Singh

  233
  Citations

• $\hbox{HfO}_{x}/\hbox{TiO}_{x}/\hbox{HfO}_{x}/ \hbox{TiO}_{x}$ Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity

  Z Fang;H Y Yu;X Li;N Singh

  231
  Citations

• Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

  Z.X. Chen;H.Y. Yu;N. Singh;N.S. Shen

  231
  Citations

• Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

  N. Singh;F. Y. Lim;W. W. Fang;S. C. Rustagi

  219
  Citations

• Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

  N. Singh;K.D. Buddharaju;S.K. Manhas;A. Agarwal

  216
  Citations

• Magnetic antidot nanostructures: effect of lattice geometry.

  C C Wang;A O Adeyeye;N Singh

  206
  Citations

• Collective spin modes in monodimensional magnonic crystals consisting of dipolarly coupled nanowires

  G. Gubbiotti;S. Tacchi;G. Carlotti;N. Singh

  175
  Citations

• Physical mechanisms of endurance degradation in TMO-RRAM

  B. Chen;Y. Lu;B. Gao;Y.H. Fu

  171
  Citations

• Magnetostatic interaction in arrays of nanometric permalloy wires: A magneto-optic Kerr effect and a Brillouin light scattering study

  G. Gubbiotti;S. Tacchi;G. Carlotti;P. Vavassori

  152
  Citations

• Excimer laser-annealed dopant segregated Schottky (ELA-DSS) Si nanowire gate-all-around (GAA) pFET with near zero effective Schottky barrier height (SBH)

  Y. K. Chin;K. L. Pey;N. Singh;G. Q. Lo

  151
  Citations

• Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

  Y Li;K Buddharaju;N Singh;G Q Lo

  143
  Citations