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Electronics and Electrical Engineering

D-Index
33
Citations
3282
World Ranking
6167
National Ranking
90

Overview

Rishu Chaujar is affiliated with Delhi Technological University in India and has contributed extensively to the field of engineering, particularly within electrical and electronic engineering. Their research spans a variety of subfields, including biomedical engineering, condensed matter physics, atomic and molecular physics, optics, and materials chemistry.

The core focus of their work lies in semiconductor devices and circuit design. Major research topics include advancements in semiconductor devices and circuit design, semiconductor materials and devices, ferroelectric and negative capacitance devices, nanowire synthesis and applications, integrated circuits and semiconductor failure analysis, GaN-based semiconductor devices and materials, and silicon carbide semiconductor technologies.

Frequent publication venues for Chaujar's research include:

  • Silicon
  • 2021 Devices for Integrated Circuit (DevIC)
  • 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)
  • Micro and Nanostructures
  • Physica Scripta

Some of their recent papers are:

  • Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, 2021, Silicon
  • TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance, 2021, Silicon
  • Rapid detection of biomolecules in a dielectric modulated GaN MOSHEMT, 2020, Journal of Materials Science Materials in Electronics
  • Numerical analysis of Mg2Si/Si heterojunction DG-TFET for low power/high performance applications: Impact of non-idealities, 2020, Superlattices and Microstructures
  • Increased efficiency of 23% for CIGS solar cell by using ITO as front contact, 2020, Materials Today Proceedings

Chaujar frequently collaborates with several coauthors, with notable partnerships including Bhavya Kumar, Ajay Kumar, Samriti Sharma, Jaya Madan, and Neha Gupta. The counts of their collaborations indicate ongoing joint research efforts.

Best Publications

  • Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

    Jaya Madan;Rishu Chaujar

  • Numerical Simulation of N + Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

    Jaya Madan;Rishu Chaujar

  • Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor

    Sona P. Kumar;Anju Agrawal;Rishu Chaujar;R.S. Gupta

  • Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

    Jaya Madan;Rishu Chaujar

  • Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell

    Rahul Pandey;Rishu Chaujar

  • TCAD RF performance investigation of Transparent Gate Recessed Channel MOSFET

    Ajay Kumar;Neha Gupta;Rishu Chaujar

  • Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior

    Jaya Madan;Rishu Chaujar

  • Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET

    Bhavya Kumar;Rishu Chaujar

  • Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET

    Jaya Madan;Rishu Chaujar

  • Reliability Issues of In 2 O 5 Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature

    Ajay Kumar;M. M. Tripathi;Rishu Chaujar

  • Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET

    Neha Gupta;Rishu Chaujar

  • Numerical simulations: Toward the design of 18.6% efficient and stable perovskite solar cell using reduced cerium oxide based ETL

    Rahul Pandey;Rahul Pandey;Anand Prakash Saini;Rishu Chaujar

  • Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design

    Ajay Kumar;Neha Gupta;Shrey Kumar Tripathi;M.M. Tripathi

  • Palladium Gate All Around - Hetero Dielectric -Tunnel FET based highly sensitive Hydrogen Gas Sensor

    Jaya Madan;Rishu Chaujar

  • Toward the design of monolithic 23.1% efficient hysteresis and moisture free perovskite/c-Si HJ tandem solar cell: a numerical simulation study

    Rahul Pandey;Anu Singla;Jaya Madan;Rajnish Sharma

  • Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

    Ajay Kumar;M. M. Tripathi;Rishu Chaujar

  • TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance

    Bhavya Kumar;Rishu Chaujar

  • Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour

    Ajay Kumar;Neha Gupta;Rishu Chaujar

  • Source/Gate Material-Engineered Double Gate TFET for improved RF and linearity performance: a numerical simulation

    Skanda Shekhar;Jaya Madan;Jaya Madan;Rishu Chaujar

  • Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

    Neha Gupta;Ajay Kumar;Rishu Chaujar

  • Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT

    Sona P. Kumar;Anju Agrawal;Rishu Chaujar;Mridula Gupta

  • TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

    R. Chaujar;R. Kaur;M. Saxena;M. Gupta

Frequent Co-Authors

Jaya Madan
Jaya Madan Chitkara University
Mridula Gupta
Mridula Gupta University of Delhi
Bansi D. Malhotra
Bansi D. Malhotra Delhi Technological University
R.K. Kotnala
R.K. Kotnala NABL India
Vidya Nand Singh
Vidya Nand Singh Council of Scientific and Industrial Research

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