His main research concerns Optoelectronics, Nanowire, Electrical engineering, Layer and Nanotechnology. His research investigates the connection between Optoelectronics and topics such as Field-effect transistor that intersect with problems in Insulator. His work carried out in the field of Nanowire brings together such families of science as Capacitance, Wafer, Inverter and Doping.
His Layer research includes elements of Threshold voltage, Transistor and Gate stack. He studied CMOS and Node that intersect with Integrated circuit layout. His Silicon on insulator research integrates issues from Metal gate and Logic gate.
His primary areas of study are Optoelectronics, Electrical engineering, Nanowire, Layer and Field-effect transistor. The study incorporates disciplines such as Gate dielectric, Electronic engineering and Gate oxide in addition to Optoelectronics. When carried out as part of a general Electrical engineering research project, his work on Transistor, CMOS, Gate stack and Static random-access memory is frequently linked to work in Communication channel, therefore connecting diverse disciplines of study.
Jeffrey W. Sleight combines subjects such as Wafer, Semiconductor and Epitaxy with his study of Nanowire. His work in the fields of Layer, such as Substrate, Semiconductor device and Etching, overlaps with other areas such as Conformal map. His Field-effect transistor study incorporates themes from Semiconductor materials, Substrate, Doping and Integrated circuit.
His primary areas of investigation include Optoelectronics, Nanowire, Layer, Wafer and Nanotechnology. The study incorporates disciplines such as Field-effect transistor, Electronic engineering and Substrate, Gate oxide in addition to Optoelectronics. To a larger extent, Jeffrey W. Sleight studies Electrical engineering with the aim of understanding Field-effect transistor.
His Layer research is multidisciplinary, incorporating perspectives in Silicon on insulator, Bipolar junction transistor and Germanium. His Wafer research incorporates themes from Trench and Doping. His Nanotechnology study integrates concerns from other disciplines, such as Electron beam processing and Transistor.
Jeffrey W. Sleight mostly deals with Optoelectronics, Nanowire, Layer, Wafer and Nanotechnology. His Optoelectronics study combines topics from a wide range of disciplines, such as Field-effect transistor, Electronic engineering, Electrical engineering and Gate oxide. His Electronic engineering research includes themes of Silicon and Dielectric.
The various areas that Jeffrey W. Sleight examines in his Gate oxide study include Gate dielectric and CMOS. His studies deal with areas such as Semiconductor device and Semiconductor as well as Nanowire. His Nanotechnology research is multidisciplinary, relying on both Band gap and Insulator.
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Stable SRAM cell design for the 32 nm node and beyond
L. Chang;D.M. Fried;J. Hergenrother;J.W. Sleight.
symposium on vlsi technology (2005)
High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
S. Bangsaruntip;G. M. Cohen;A. Majumdar;Y. Zhang.
international electron devices meeting (2009)
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
S. Bangsaruntip;A. Majumdar;G. M. Cohen;S. U. Engelmann.
symposium on vlsi technology (2010)
High-performance cmos soi device on hybrid crystal-oriented substrates
Bruce B. Doris;Kathryn W. Guarini;Meikei Ieong;Shreesh Narasimha.
Nanowire field-effect transistors
Sarunya Bangsaruntip;Guy M. Cohen;Shreesh Narasimha;Jeffrey W. Sleight.
Hybrid CMOS technology with nanowire devices and double gated planar devices
Sarunya Bangsaruntip;Josephine B. Chang;Leland Chang;Jeffrey W. Sleight.
Field-effect transistor inverter and fabricating method thereof
Josephine Chang;Paul Chang;Guillorn Michael A;Jeffrey Sleight.
Measurement of Carrier Mobility in Silicon Nanowires
Oki Gunawan;Lidija Sekaric;Amlan Majumdar;Michael Rooks.
Nano Letters (2008)
Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs
Sarunya Bangsaruntip;Guy M Cohen;Amlan Majumdar;Jeffrey W Sleight.
IEEE Electron Device Letters (2010)
Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement
Kerry Bernstein;Min Yang.
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