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Electronics and Electrical Engineering

D-Index
30
Citations
4525
World Ranking
6755
National Ranking
2196

Overview

Terence B. Hook is affiliated with IBM in the United States, where they conduct research in the field of engineering, with a primary focus on electrical and electronic engineering. Their work emphasizes advancements in semiconductor technology and integrated circuit design.

The main topics of Terence B. Hook's research include:

  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis

They have contributed scholarly work primarily published in the venue IEEE Transactions on Electron Devices.

One of their recent papers is titled Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating, published in 2020 in IEEE Transactions on Electron Devices.

Terence B. Hook collaborates frequently with several researchers including:

  • Charu Gupta
  • Anshul Gupta
  • Reinaldo A. Vega
  • Abhisek Dixit

Their research involves detailed analysis of semiconductor device performance and reliability, focusing on effects such as hot-carrier degradation in nanoscale device architectures. This work contributes to understanding how semiconductor devices behave under electrical stress and how these phenomena affect device stability and circuit functionality.

Best Publications

  • Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

    N. Loubet;T. Hook;P. Montanini;C.-W. Yeung

  • Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

    Terence B. Hook

  • A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

    R. Xie;P. Montanini;K. Akarvardar;N. Tripathi

  • Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

    Henry A. Bonges;David L. Harmon;Terence B. Hook;Wing L. Lai

  • Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

    Seong-Dong Kim;Michael Guillorn;Isaac Lauer;Phil Oldiges

  • Lateral ion implant straggle and mask proximity effect

    T.B. Hook;J. Brown;P. Cottrell;E. Adler

  • High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

    V. Chan;R. Rengarajan;N. Rovedo;Wei Jin

  • The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

    T.B. Hook;E. Adler;F. Guarin;J. Lukaitis

  • CMOS well structure and method of forming the same

    Wilfried Haensch;Terence B. Hook;Louis C. Hsu;Rajiv V. Joshi

  • High performance and low power transistors integrated in 65nm bulk CMOS technology

    Z. Luo;A. Steegen;M. Eller;R. Mann

  • Enchanced multi-threshold (MTCMOS) circuits using variable well bias

    S.V. Kosonocky;M. Irnmediato;P. Cottrell;T. Hook

  • A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

    K. I. Seo;B. Haran;D. Gupta;D. Guo

  • Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

    Zhi Cheng Yuan;Shahriar Rizwan;Michael Wong;Kyle Holland

  • Channel doping impact on FinFETs for 22nm and beyond

    C.-H. Lin;R. Kambhampati;R. J. Miller;T. B. Hook

  • Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

    Chuan Hsi Liu;Ming T. Lee;Chih Yung Lin;Jenkon Chen

  • Physically Unclonable Function Implemented Through Threshold Voltage Comparison

    Joel T. Ficke;William E. Hall;Terence B. Hook;Michael A. Sperling

  • Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

    C.H. Liu;M.T. Lee;Chih-Yung Lin;J. Chen

  • UTBB FDSOI transistors with dual STI for a multi-V t strategy at 20nm node and below

    L. Grenouillet;M. Vinet;J. Gimbert;B. Giraud

  • Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

    Xiaobin Yuan;Jae-Eun Park;Jing Wang;Enhai Zhao

  • The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

    T.G. Ference;J.S. Burnham;W.F. Clark;T.B. Hook

  • Hot‐electron induced interface traps in metal/SiO2/Si capacitors: The effect of gate‐induced strain

    Terence B. Hook;T. P. Ma

  • Impact of back bias on ultra-thin body and BOX (UTBB) devices

    Q. Liu;F. Monsieur;A. Kumar;T. Yamamoto

  • FINFET technology featuring high mobility SiGe channel for 10nm and beyond

    D. Guo;G. Karve;G. Tsutsui;K-Y Lim

Frequent Co-Authors

Bruce B. Doris
Bruce B. Doris IBM (United States)
Ali Khakifirooz
Ali Khakifirooz Intel (United States)
Kangguo Cheng
Kangguo Cheng IBM (United States)
Douglas D. Coolbaugh
Douglas D. Coolbaugh University at Albany, State University of New York
Edmund J. Sprogis
Edmund J. Sprogis IBM (United States)
Matthew J. Breitwisch
Matthew J. Breitwisch IBM (United States)
Robert H. Dennard
Robert H. Dennard IBM (United States)
Vamsi K. Paruchuri
Vamsi K. Paruchuri IBM (United States)
Vijay Narayanan
Vijay Narayanan IBM (United States)
Michael A. Guillorn
Michael A. Guillorn IBM (United States)

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