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Vamsi K. Paruchuri

Vamsi K. Paruchuri

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
6460
World Ranking
4880
National Ranking
1705

Overview

Vamsi K. Paruchuri is affiliated with IBM in the United States, contributing research primarily within the fields of Computer Science, Engineering, and Materials Science. Their body of work encompasses a variety of subfields, including Information Systems, Signal Processing, Computer Networks and Communications, Mechanical Engineering, and Materials Chemistry.

The scientist's research topics cover several advanced domains such as User Authentication and Security Systems, Biometric Identification and Security, Advanced Authentication Protocols Security, Metallurgical Processes and Thermodynamics, Solidification and Crystal Growth Phenomena, Aluminum Alloy Microstructure Properties, and Blockchain Technology Applications and Security.

Recent publication activity includes a paper titled "Phase field simulation of segregation and precipitates formation during steel solidification", published in 2023. This work appeared in the IOP Conference Series Materials Science and Engineering and has been cited twice. The study focuses on metallurgical processes relevant to understanding steel solidification patterns.

  • Sriram Bobba
  • Begoña Santillana
  • Ulrich Prahl
  • Ali Bakhshi

Vamsi K. Paruchuri has collaborated with frequent coauthors including Sriram Bobba, Begoña Santillana, Ulrich Prahl, and Ali Bakhshi. These partnerships reflect interdisciplinary efforts linking Computer Science and Engineering disciplines with applied materials research.

  • IOP Conference Series Materials Science and Engineering

The scientist's publications are concentrated in venues such as the IOP Conference Series Materials Science and Engineering, underscoring engagement with materials-oriented engineering research communities. Their work bridges computational techniques and practical applications in physical sciences and security systems.

Best Publications

  • Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

    N. Loubet;T. Hook;P. Montanini;C.-W. Yeung

  • A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

    S. Zafar;Y.H. Kim;V. Narayanan;C. Cabral

  • Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

    H. Kawasaki;V. S. Basker;T. Yamashita;C.-H. Lin

  • Hafnium oxide gate dielectrics on sulfur-passivated germanium

    Martin M. Frank;Steven J. Koester;Matthew Copel;John A. Ott

  • A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

    R. Xie;P. Montanini;K. Akarvardar;N. Tripathi

  • Random asynchronous wakeup protocol for sensor networks

    V. Paruchuri;S. Basavaraju;A. Durresi;R. Kannan

  • Optimized broadcast protocol for sensor networks

    A. Durresi;V.K. Paruchuri;S.S. Iyengar;R. Kannan

  • Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

    S. Guha;S. Guha;V. K. Paruchuri;M. Copel;V. Narayanan

  • Securing powerline communications

    V. Paruchuri;A. Durresi;M. Ramesh

  • SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS

    Nestor A. Bojarczuk;Cyril Cabral;Eduard A. Cartier;Matthew W. Copel

  • Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos

    Nestor A. Bojarczuk;Michael P. Chudzik;Matthew W. Copel;Supratik Guha

  • A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

    S. Krishnan;U. Kwon;N. Moumen;M.W. Stoker

  • Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/

    E. Cartier;F.R. McFeely;V. Narayanan;P. Jamison

  • High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

    M. Chudzik;B. Doris;R. Mo;J. Sleight

  • A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

    V. S. Basker;T. Standaert;H. Kawasaki;C.-C. Yeh

  • Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

    V. Narayanan;V.K. Paruchuri;N.A. Bojarczuk;B.P. Linder

  • Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

    F. Andrieu;O. Weber;J. Mazurier;O. Thomas

  • Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack

    E. Cartier;B. P. Linder;V. Narayanan;V. K. Paruchuri

  • A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

    K. I. Seo;B. Haran;D. Gupta;D. Guo

  • 22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

    B.S. Haran;A. Kumar;L. Adam;J. Chang

Frequent Co-Authors

Vijay Narayanan
Vijay Narayanan IBM (United States)
Bruce B. Doris
Bruce B. Doris IBM (United States)
Michael P. Chudzik
Michael P. Chudzik IBM (United States)
Leonard Barolli
Leonard Barolli Fukuoka Institute of Technology
Eduard A. Cartier
Eduard A. Cartier IBM (United States)
Supratik Guha
Supratik Guha Argonne National Laboratory
Martin M. Frank
Martin M. Frank IBM (United States)
Matthew Copel
Matthew Copel IBM (United States)
Sufi Zafar
Sufi Zafar IBM (United States)
Alexander Reznicek
Alexander Reznicek IBM (United States)

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