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Naoto Horiguchi

Naoto Horiguchi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
6900
World Ranking
4863
National Ranking
104

Overview

Naoto Horiguchi is affiliated with Imec in Belgium and has a significant research footprint in the field of engineering, focusing primarily on electrical and electronic engineering. Their work spans various subfields including biomedical engineering, atomic and molecular physics and optics, materials chemistry, and electronic, optical, and magnetic materials.

The scientist's research topics cover several key areas such as semiconductor materials and devices, advancements in semiconductor devices and circuit design, integrated circuits and semiconductor failure analysis, nanowire synthesis and applications, thin-film transistor technologies, ferroelectric and negative capacitance devices, and semiconductor materials and interfaces.

Horiguchi has contributed to numerous papers, including the following notable recent publications:

  • "Nondestructive, high-resolution, chemically specific 3D nanostructure characterization using phase-sensitive EUV imaging reflectometry," 2021, Science Advances
  • "Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling," 2020, IEEE Transactions on Electron Devices
  • "Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond," 2021, 2021 IEEE International Electron Devices Meeting (IEDM)
  • "Low-Frequency Noise in Vertically Stacked Si n-Channel Nanosheet FETs," 2020, IEEE Electron Device Letters
  • "Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures," 2022, 2022 International Electron Devices Meeting (IEDM)

Their frequent coauthors include:

  • Hans Mertens
  • E. Dentoni Litta
  • A. Veloso
  • Roger Loo
  • R. Ritzenthaler

Horiguchi's publications are often found in specific venues related to electrical engineering and semiconductor research, such as:

  • ECS Meeting Abstracts
  • IEEE Transactions on Electron Devices
  • ECS Transactions
  • 2022 International Electron Devices Meeting (IEDM)
  • Solid-State Electronics

Best Publications

  • Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

    H. Mertens;R. Ritzenthaler;A. Hikavyy;M. S. Kim

  • The Complementary FET (CFET) for CMOS scaling beyond N3

    J. Ryckaert;P. Schuddinck;P. Weckx;G. Bouche

  • Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

    H. Mertens;R. Ritzenthaler;A. Chasin;T. Schram

  • Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

    H. Mertens;R. Ritzenthaler;V. Pena;G. Santoro

  • Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

    J. Franco;B. Kaczer;M. Toledano-Luque;Ph. J. Roussel

  • Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

    S. B. Samavedam;J. Ryckaert;E. Beyne;K. Ronse

  • Novel forksheet device architecture as ultimate logic scaling device towards 2nm

    P. Weckx;M. Gupta;Y. Oniki;L.-A. Ragnarsson

  • Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

    A. Redolfi;S. Kubicek;R. Rooyackers;M.-S. Kim

  • First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

    S. Subramanian;M. Hosseini;T. Chiarella;S. Sarkar

  • Response of a single trap to AC negative Bias Temperature stress

    M. Toledano-Luque;B. Kaczer;Ph.J. Roussel;T. Grasser

  • Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

    R. Ritzenthaler;H. Mertens;V. Pena;G. Santoro

  • Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

    Hao Yu;Marc Schaekers;Tom Schram;Erik Rosseel

  • Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$ -FinFETs

    Moonju Cho;Philippe Roussel;Ben Kaczer;Robin Degraeve

  • QUANTUM DOT INFRARED PHOTODETECTOR USING MODULATION DOPED INAS SELF-ASSEMBLED QUANTUM DOTS

    Naoto Horiguchi;Toshiro Futatsugi;Yoshiaki Nakata;Naoki Yokoyama

  • Microstructure and electrical properties of Sn nanocrystals in thin, thermally grown SiO2 layers formed via low energy ion implantation

    Anri Nakajima;Toshiro Futatsugi;Hiroshi Nakao;Tatsuya Usuki

  • Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

    K. Goto;S. Satoh;H. Ohta;S. Fukuta

  • Formation of Sn nanocrystals in thin SiO2 film using low-energy ion implantation

    Anri Nakajima;Toshiro Futatsugi;Naoto Horiguchi;Naoki Yokoyama

  • 1.5×10−9 Ωcm2 Contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation

    H. Yu;M. Schaekers;E. Rosseel;A. Peter

  • Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

    A. Veloso;T. Huynh-Bao;P. Matagne;D. Jang

  • Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

    Niamh Waldron;Gang Wang;Ngoc Duy Nguyen;Tommaso Orzali

  • Characterization of Epitaxial Si:C:P and Si:P Layers for Source/Drain Formation in Advanced Bulk FinFETs

    Erik Rosseel;Harald Benjamin Profijt;Andriy Yakovitch Hikavyy;John Tolle

  • Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

    M. Garcia Bardon;Y. Sherazi;P. Schuddinck;D. Jang

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