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Jacopo Franco

Jacopo Franco

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
6202
World Ranking
4902
National Ranking
106

Overview

Jacopo Franco is affiliated with Imec in Belgium and has contributed extensively to the engineering field, particularly in the domain of electrical and electronic engineering. Their work spans multiple subfields including atomic and molecular physics and optics, electronic, optical and magnetic materials, materials chemistry, and condensed matter physics.

The primary focus of Jacopo Franco's research lies in semiconductor materials and devices, with numerous publications addressing advancements in semiconductor devices and circuit design. They have also covered topics related to integrated circuits and semiconductor failure analysis, thin-film transistor technologies, silicon and solar cell technologies, ferroelectric and negative capacitance devices, and copper interconnects and reliability.

Frequent co-authors of Jacopo Franco include B. Kaczer, Naoto Horiguchi, Adrian Chasin, Ingrid De Wolf, and E. Dentoni Litta.

Publication venues where Jacopo Franco has regularly contributed include:

  • IEEE Transactions on Electron Devices
  • Solid-State Electronics
  • 2022 IEEE International Reliability Physics Symposium (IRPS)
  • IEEE Transactions on Device and Materials Reliability
  • 2021 IEEE International Electron Devices Meeting (IEDM)

Recent notable papers authored or co-authored by Jacopo Franco include:

  • Understanding and modelling the PBTI reliability of thin-film IGZO transistors, 2021, 2021 IEEE International Electron Devices Meeting (IEDM)
  • Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures, 2023, IEEE Transactions on Electron Devices
  • Comphy v3.0-A compact-physics framework for modeling charge trapping related reliability phenomena in MOS devices, 2023, Microelectronics Reliability
  • Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
  • Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs, 2022, 2022 IEEE International Reliability Physics Symposium (IRPS)

Best Publications

  • The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps

    T. Grasser;B. Kaczer;W. Goes;H. Reisinger

  • Origin of NBTI variability in deeply scaled pFETs

    B. Kaczer;T. Grasser;Ph. J. Roussel;J. Franco

  • Comphy — A compact-physics framework for unified modeling of BTI

    Gerhard Rzepa;Jacopo Franco;Barry J. O'Sullivan;A. Subirats

  • Switching oxide traps as the missing link between negative bias temperature instability and random telegraph noise

    T. Grasser;H. Reisinger;W. Goes;Th. Aichinger

  • Recent advances in understanding the bias temperature instability

    T. Grasser;B. Kaczer;W. Goes;H. Reisinger

  • From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation

    M. Toledano-Luque;B. Kaczer;J. Franco;Ph.J. Roussel

  • Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

    J. Franco;B. Kaczer;M. Toledano-Luque;Ph. J. Roussel

  • A unified perspective of RTN and BTI

    Tibor Grasser;Karsten Rott;H. Reisinger;M. Waltl

  • Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

    Moonju Cho;Jae-Duk Lee;M. Aoulaiche;B. Kaczer

  • The ‘permanent’ component of NBTI: Composition and annealing

    T. Grasser;Th. Aichinger;G. Pobegen;H. Reisinger

  • SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI

    J. Franco;B. Kaczer;P. J. Roussel;J. Mitard

  • Predictive Hot-Carrier Modeling of n-Channel MOSFETs

    Markus Bina;Stanislav Tyaginov;Jacopo Franco;Karl Rupp

  • Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs

    Stanislav Tyaginov;Markus Jech;Jacopo Franco;Prateek Sharma

  • Response of a single trap to AC negative Bias Temperature stress

    M. Toledano-Luque;B. Kaczer;Ph.J. Roussel;T. Grasser

  • Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$ -FinFETs

    Moonju Cho;Philippe Roussel;Ben Kaczer;Robin Degraeve

  • Toward Understanding Positive Bias Temperature Instability in Fully Recessed-Gate GaN MISFETs

    Tian-Li Wu;Jacopo Franco;Denis Marcon;Brice De Jaeger

  • Understanding and modelling the PBTI reliability of thin-film IGZO transistors

    Unknown

  • Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

    Tian-Li Wu;Denis Marcon;Benoit Bakeroot;Brice De Jaeger

  • Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO 2 /HfO 2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

    J. Franco;B. Kaczer;Ph J. Roussel;J. Mitard

  • Degradation of time dependent variability due to interface state generation

    M. Toledano-Luque;B. Kaczer;J. Franco;Ph J. Roussel

  • Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

    N. Waldron;S. Sioncke;J. Franco;L. Nyns

  • A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

    Ben Kaczer;Jacopo Franco;Pieter Weckx;Philippe Roussel

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