Souvik Mahapatra spends much of his time researching Negative-bias temperature instability, MOSFET, Electronic engineering, Analytical chemistry and Duty cycle. His Negative-bias temperature instability research is multidisciplinary, relying on both Ac frequency and Insulator. His MOSFET study incorporates themes from Optoelectronics, SILC, Condensed matter physics and Nitriding.
His Electronic engineering research is multidisciplinary, incorporating elements of PMOS logic, Gate insulator and Reliability. The various areas that Souvik Mahapatra examines in his Analytical chemistry study include Threshold voltage, Positive bias temperature instability, Electron trapping and Gate oxide. His research integrates issues of Mechanics and Logic gate in his study of Duty cycle.
Negative-bias temperature instability, Optoelectronics, Electronic engineering, MOSFET and Electrical engineering are his primary areas of study. His Negative-bias temperature instability research integrates issues from Metal gate, Condensed matter physics and Duty cycle. In the field of Optoelectronics, his study on Dielectric overlaps with subjects such as Trap.
In his study, which falls under the umbrella issue of Electronic engineering, Transistor is strongly linked to Reliability. Souvik Mahapatra works mostly in the field of MOSFET, limiting it down to topics relating to Analytical chemistry and, in certain cases, Molecular physics and Gate dielectric. The Electrical engineering study combines topics in areas such as Quantum tunnelling and Hot electron.
His scientific interests lie mostly in Negative-bias temperature instability, Threshold voltage, Condensed matter physics, Metal gate and Hot carrier degradation. His study focuses on the intersection of Negative-bias temperature instability and fields such as Thermionic emission with connections in the field of Gate dielectric and P channel. As a part of the same scientific study, he usually deals with the Threshold voltage, concentrating on Ring oscillator and frequently concerns with NMOS logic, PMOS logic and Coupling.
He works mostly in the field of Metal gate, limiting it down to topics relating to Optoelectronics and, in certain cases, Field-effect transistor and Saturation, as a part of the same area of interest. His Hot carrier degradation study necessitates a more in-depth grasp of MOSFET. His research in Voltage intersects with topics in Electronic engineering and Logic gate.
His primary areas of investigation include Negative-bias temperature instability, Threshold voltage, Condensed matter physics, Germanium and Metal gate. His biological study spans a wide range of topics, including Logic gate and Electronic band structure. His study with Threshold voltage involves better knowledge in Voltage.
His studies deal with areas such as Universality and Electronic engineering as well as Voltage. His Condensed matter physics research includes elements of Field-effect transistor, Non-volatile memory, Ferroelectricity and Capacitor. His work in Germanium tackles topics such as Silicon-germanium which are related to areas like Activation energy.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
A comprehensive model of PMOS NBTI degradation
Muhammad Ashraful Alam;S. Mahapatra.
Microelectronics Reliability (2005)
A comprehensive model for PMOS NBTI degradation: Recent progress.
Muhammad Ashraful Alam;Haldun Kufluoglu;D. Varghese;D. Varghese;S. Mahapatra.
Microelectronics Reliability (2007)
Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation
A.E. Islam;H. Kufluoglu;D. Varghese;S. Mahapatra.
IEEE Transactions on Electron Devices (2007)
A Comparative Study of Different Physics-Based NBTI Models
S. Mahapatra;N. Goel;S. Desai;S. Gupta.
IEEE Transactions on Electron Devices (2013)
Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs
S. Mahapatra;P.B. Kumar;M.A. Alam.
IEEE Transactions on Electron Devices (2004)
On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress
S. Mahapatra;D. Saha;D. Varghese;P.B. Kumar.
IEEE Transactions on Electron Devices (2006)
Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance
Kai Ni;Pankaj Sharma;Jianchi Zhang;Matthew Jerry.
IEEE Transactions on Electron Devices (2018)
On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?
S. Mahapatra;K. Ahmed;D. Varghese;A.E. Islam.
international reliability physics symposium (2007)
A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery
S. Mahapatra;A. E. Islam;S. Deora;V. D. Maheta.
international reliability physics symposium (2011)
On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications
D. Varghese;D. Saha;S. Mahapatra;K. Ahmed.
international electron devices meeting (2005)
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