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Electronics and Electrical Engineering

D-Index
43
Citations
8352
World Ranking
3869
National Ranking
37

Overview

Souvik Mahapatra is affiliated with the Indian Institute of Technology Bombay in India. Their research primarily focuses on the field of engineering, with a specific emphasis on electrical and electronic engineering. Contributions also extend to materials chemistry, atomic and molecular physics, optics, computer networks and communications, and electronic, optical, and magnetic materials.

The main topics of their work include semiconductor materials and devices, advancements in semiconductor devices and circuit design, ferroelectric and negative capacitance devices, silicon carbide semiconductor technologies, integrated circuits and semiconductor failure analysis, electrostatic discharge in electronics, and advanced data storage technologies.

Publication venues frequently hosting their research include:

  • IEEE Transactions on Electron Devices
  • Solid-State Electronics
  • IEEE Transactions on Device and Materials Reliability
  • IEEE Journal of the Electron Devices Society
  • 2022 IEEE International Reliability Physics Symposium (IRPS)

Frequent coauthors collaborating with Souvik Mahapatra are:

  • Nilotpal Choudhury
  • Narendra Parihar
  • Uma Sharma
  • Himanshu Diwakar
  • Karansingh Thakor

Recent papers authored or coauthored by them include:

  • "Ultrathin ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors," 2022, Nature
  • "A Review of Hot Carrier Degradation in n-Channel MOSFETs-Part I: Physical Mechanism," 2020, IEEE Transactions on Electron Devices
  • "Modeling of NBTI Using BAT Framework: DC-AC Stress-Recovery Kinetics, Material, and Process Dependence," 2020, IEEE Transactions on Device and Materials Reliability
  • "A Review of Hot Carrier Degradation in n-Channel MOSFETs-Part II: Technology Scaling," 2020, IEEE Transactions on Electron Devices
  • "A Generic Trap Generation Framework for MOSFET Reliability-Part I: Gate Only Stress-BTI, SILC, and TDDB," 2023, IEEE Transactions on Electron Devices

Best Publications

  • A comprehensive model of PMOS NBTI degradation

    Muhammad Ashraful Alam;S. Mahapatra

  • Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

    Kai Ni;Pankaj Sharma;Jianchi Zhang;Matthew Jerry

  • A comprehensive model for PMOS NBTI degradation: Recent progress.

    Muhammad Ashraful Alam;Haldun Kufluoglu;D. Varghese;D. Varghese;S. Mahapatra

  • A Comparative Study of Different Physics-Based NBTI Models

    S. Mahapatra;N. Goel;S. Desai;S. Gupta

  • Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

    A.E. Islam;H. Kufluoglu;D. Varghese;S. Mahapatra

  • Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

    S. Mahapatra;P.B. Kumar;M.A. Alam

  • On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

    S. Mahapatra;D. Saha;D. Varghese;P.B. Kumar

  • On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?

    S. Mahapatra;K. Ahmed;D. Varghese;A.E. Islam

  • A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery

    S. Mahapatra;A. E. Islam;S. Deora;V. D. Maheta

  • On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications

    D. Varghese;D. Saha;S. Mahapatra;K. Ahmed

  • Controversial issues in negative bias temperature instability

    James H. Stathis;Souvik Mahapatra;Tibor Grasser

  • BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation

    Narendra Parihar;Nilesh Goel;Subhadeep Mukhopadhyay;Souvik Mahapatra

  • A consistent physical framework for N and P BTI in HKMG MOSFETs

    Kaustubh Joshi;Subhadeep Mukhopadhyay;Nilesh Goel;Souvik Mahapatra

  • Isolation of NBTI Stress Generated Interface Trap and Hole-Trapping Components in PNO p-MOSFETs

    S. Mahapatra;V.D. Maheta;A.E. Islam;M.A. Alam

  • Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen

    S. Mahapatra;P. Bharath Kumar;T.R. Dalei;D. Sana

  • Negative bias temperature instability in CMOS devices

    S. Mahapatra;M. A. Alam;P. Bharath Kumar;T. R. Dalei

  • Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

    S. Mahapatra;C.D. Parikh;V.R. Rao;C.R. Viswanathan

  • A predictive reliability model for PMOS bias temperature degradation

    S. Mahapatra;M.A. Alam

  • Hole energy dependent interface trap generation in MOSFET Si/SiO/sub 2/ interface

    D. Varghese;S. Mahapatra;M.A. Alam

  • CHISEL flash EEPROM. I. Performance and scaling

    S. Mahapatra;S. Shukuri;J. Bude

  • Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

    S. Mahapatra;M.A. Alam

Frequent Co-Authors

Muhammad A. Alam
Muhammad A. Alam Purdue University West Lafayette
V. Ramgopal Rao
V. Ramgopal Rao Indian Institute of Technology Bombay
Suman Datta
Suman Datta Georgia Institute of Technology
Jorg Henkel
Jorg Henkel Karlsruhe Institute of Technology
James H. Stathis
James H. Stathis IBM (United States)
Saurabh Lodha
Saurabh Lodha Indian Institute of Technology Bombay
Jason C. S. Woo
Jason C. S. Woo University of California, Los Angeles
Yogesh Singh Chauhan
Yogesh Singh Chauhan Indian Institute of Technology Kanpur
Elyse Rosenbaum
Elyse Rosenbaum University of Illinois at Urbana-Champaign

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