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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
43
Citations
7843
World Ranking
3888
National Ranking
1399

Overview

Jason C. S. Woo is affiliated with the University of California, Los Angeles in the United States. Their research spans the fields of Engineering and Neuroscience, with a focus on Electrical and Electronic Engineering, Cognitive Neuroscience, Biomedical Engineering, Condensed Matter Physics, and Electronic, Optical and Magnetic Materials.

Their work primarily addresses topics such as advancements in semiconductor devices and circuit design, semiconductor materials and devices, neural and behavioral psychology studies, nanowire synthesis and applications, integrated circuits and semiconductor failure analysis, memory processes and influences, and EEG and brain-computer interfaces.

Jason C. S. Woo has contributed to several recent scientific papers, including:

  • Vertical P-TFET With a P-Type SiGe Pocket (2020), published in IEEE Transactions on Electron Devices
  • Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs (2021), published in IEEE Transactions on Electron Devices
  • Tracing the emergence of the memorability benefit (2023), published in Cognition
  • Selective-Area Growth of Hexagonal-to-Cubic GaN as an n-Type Metal-Oxide-Semiconductor Field-Effect Transistor Drain on a Nanogrooved Si(100) Substrate (2024), published in Crystal Growth & Design
  • Tracing the Emergence of the Memorability Benefit (2022), published in SSRN Electronic Journal

Frequent co-authors collaborating with Jason C. S. Woo include:

  • Weicong Li
  • Greer Gillies
  • Dirk B. Walther
  • Jonathan S. Cant
  • Keisuke Fukuda

The most common publication venues for their work are:

  • IEEE Transactions on Electron Devices
  • Cognition
  • Crystal Growth & Design
  • SSRN Electronic Journal

Jason C. S. Woo's research intersects multiple disciplines, underpinning the development and understanding of semiconductor technologies as well as exploring cognitive and neural processes related to memory and brain-computer interfaces.

Best Publications

  • The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

    B. Cheng;M. Cao;R. Rao;A. Inani

  • The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

    V. Nagavarapu;R. Jhaveri;J.C.S. Woo

  • Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

    R Jhaveri;V Nagavarapu;J C S Woo

  • A MEMS based amperometric detector for E. coli bacteria using self-assembled monolayers.

    Jen-Jr Gau;Esther H Lan;Bruce Dunn;Chih-Ming Ho

  • High-gain lateral bipolar action in a MOSFET structure

    S. Verdonckt-Vandebroek;S.S. Wong;J.C.S. Woo;P.K. Ko

  • Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS

    D.K. Nayak;J.C.S. Woo;J.S. Park;K. Wang

  • Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides

    D. Dimitropoulos;R. Jhaveri;R. Claps;J. C. S. Woo

  • Salicidation process using NiSi and its device application

    F. Deng;R. A. Johnson;P. M. Asbeck;S. S. Lau

  • High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si

    Deepak K. Nayak;Jason C. S. Woo;Jin S. Park;Kang L. Wang

  • Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

    Seong-Dong Kim;Cheol-Min Park;J.C.S. Woo

  • Complementary field effect transistors having strained superlattice structure

    Kang L. Wang;Jason C. Woo

  • Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing

    Hsu-Yu Chang;B. Adams;Po-Yen Chien;Jiping Li

  • Large scale pattern graphene electrode for high performance in transparent organic single crystal field-effect transistors.

    Wei Liu;Biyun Li Jackson;Jing Zhu;Cong-Qin Miao

  • TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling

    Seong-Dong Kim;H. Wada;J.C.S. Woo

  • Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis

    Seong-Dong Kim;Cheol-Min Park;J.C.S. Woo

  • Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation

    Seong-Dong Kim;Cheol-Min Park;J.C.S. Woo

  • Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

    R. Jhaveri;V. Nagavarapu;J.C.S. Woo

  • Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

    M. Song;K.P. MacWilliams;J.C.S. Woo

  • Rapid isothermal processing of strained GeSi layers

    D.K. Nayak;K. Kamjoo;J.S. Park;J.C.S. Woo

  • Contact resistance in top-gated graphene field-effect transistors

    Bo-Chao Huang;Ming Zhang;Yanjie Wang;Jason Woo

Frequent Co-Authors

Kang L. Wang
Kang L. Wang University of California, Los Angeles
Ya-Hong Xie
Ya-Hong Xie University of California, Los Angeles
V. Ramgopal Rao
V. Ramgopal Rao Indian Institute of Technology Bombay
Roland Scholz
Roland Scholz Max Planck Society
Souvik Mahapatra
Souvik Mahapatra Indian Institute of Technology Bombay
James D. Plummer
James D. Plummer Stanford University
Cheol-Min Park
Cheol-Min Park Kumoh National Institute of Technology
Chih-Kong Ken Yang
Chih-Kong Ken Yang University of California, Los Angeles
Subramanian S. Iyer
Subramanian S. Iyer University of California, Los Angeles
Eduard A. Cartier
Eduard A. Cartier IBM (United States)

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