2020 - IEEE Medal of Honor For a distinguished career of developing and putting into practice semiconductor models, particularly 3-D device structures, that have helped keep Moore's Law going over many decades.
2015 - Fellow, National Academy of Inventors
2012 - Fellow, The World Academy of Sciences
2011 - Semiconductor Industry Association University Researcher Award
2009 - IEEE Jun-ichi Nishizawa Medal "For technical contributions to MOS device reliability, scaling of CMOS and compact device modeling."
2002 - IEEE Donald O. Pederson Award in Solid-State Circuits "For contributions to MOSFET physics and development of the BSIM model for CMOS circuit simulation."
1998 - Monie A. Ferst Award, Sigma Xi
1997 - Member of the National Academy of Engineering For contributions to the modeling integration-circuit devices and to the reliability and performance of VLSI systems.
1990 - IEEE Fellow For contributions to the understanding of hot-electron effects in MOS devices.
Chenming Hu mainly focuses on Optoelectronics, MOSFET, Electrical engineering, Transistor and Electronic engineering. His work deals with themes such as Field-effect transistor, Gate dielectric, Electrode and Gate oxide, which intersect with Optoelectronics. His MOSFET study combines topics from a wide range of disciplines, such as Electron mobility, Capacitance, Leakage, Threshold voltage and Silicon on insulator.
Chenming Hu combines subjects such as Substrate, Communication channel and Doping with his study of Electrical engineering. His research investigates the link between Transistor and topics such as Semiconductor that cross with problems in Insulator and Semiconductor device. The study incorporates disciplines such as Noise and Integrated circuit in addition to Electronic engineering.
Chenming Hu spends much of his time researching Optoelectronics, Electrical engineering, MOSFET, Electronic engineering and Transistor. His Optoelectronics research is multidisciplinary, relying on both Gate dielectric and Gate oxide. As a member of one scientific family, Chenming Hu mostly works in the field of Gate dielectric, focusing on Electrode and, on occasion, Layer.
His Electrical engineering study frequently links to adjacent areas such as Oxide. In his research, Negative impedance converter is intimately related to Capacitance, which falls under the overarching field of MOSFET. As a part of the same scientific family, he mostly works in the field of Electronic engineering, focusing on Reliability and, on occasion, Electromigration.
Chenming Hu mostly deals with Optoelectronics, MOSFET, Electronic engineering, Logic gate and Capacitance. The Optoelectronics study combines topics in areas such as Field-effect transistor, Transistor and Electrical engineering. Chenming Hu has included themes like Silicon on insulator and Scaling in his Transistor study.
Chenming Hu is interested in Gate oxide, which is a branch of Electrical engineering. The various areas that he examines in his MOSFET study include Computational physics, Doping, Flicker noise and CMOS, Semiconductor device modeling. His studies in Electronic engineering integrate themes in fields like BSIM and Reliability.
His primary scientific interests are in Optoelectronics, MOSFET, Electrical engineering, Electronic engineering and Logic gate. The concepts of his Optoelectronics study are interwoven with issues in Field-effect transistor, Nanotechnology and Gate oxide. His MOSFET study necessitates a more in-depth grasp of Transistor.
His work carried out in the field of Electrical engineering brings together such families of science as Power and Parasitic capacitance. His Electronic engineering research is multidisciplinary, incorporating perspectives in Node and BSIM. His Logic gate research integrates issues from Electronic circuit, Capacitance, Gate control, Negative impedance converter and Threshold voltage.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
D. Hisamoto;Wen-Chin Lee;J. Kedzierski;H. Takeuchi.
IEEE Transactions on Electron Devices (2000)
Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement
Chenming Hu;Simon C. Tam;Fu-Chieh Hsu;Ping-Keung Ko.
IEEE Journal of Solid-state Circuits (1985)
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
K.K. Hung;P.K. Ko;C. Hu;Y.C. Cheng.
IEEE Transactions on Electron Devices (1990)
Sub 50-nm FinFET: PMOS
Xuejue Huang;Wen-Chin Lee;Charles Kuo;D. Hisamoto.
international electron devices meeting (1999)
FinFET scaling to 10 nm gate length
Bin Yu;Leland Chang;S. Ahmed;Haihong Wang.
international electron devices meeting (2002)
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
Y. Cao;T. Sato;M. Orshansky;D. Sylvester.
custom integrated circuits conference (2000)
MoS2 Transistors With 1-nanometer Gate Lengths
Sujay B. Desai;Sujay B. Desai;Surabhi R. Madhvapathy;Surabhi R. Madhvapathy;Angada B. Sachid;Angada B. Sachid;Juan Pablo Llinas;Juan Pablo Llinas.
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu;Tsu-Jae King;Vivek Subramanian;Leland Chang.
Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation
K.F. Schuegraf;Chenming Hu.
IEEE Transactions on Electron Devices (1994)
MOS capacitance measurements for high-leakage thin dielectrics
K.J. Yang;Chenming Hu.
IEEE Transactions on Electron Devices (1999)
Profile was last updated on December 6th, 2021.
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