World's Best Scientists 2026 revealed!
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Electronics and Electrical Engineering
USA
2026
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Materials Science
USA
2026

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
150
Citations
85423
World Ranking
17
National Ranking
8

Materials Science

D-Index
144
Citations
75848
World Ranking
205
National Ranking
86

Research.com Recognitions

  • 2026 - Research.com Electronics and Electrical Engineering in United States Leader Award
  • 2026 - Research.com Materials Science in United States Leader Award
  • 2025 - Research.com Electronics and Electrical Engineering in United States Leader Award
  • 2025 - Research.com Materials Science in United States Leader Award
  • 2022 - Research.com Electronics and Electrical Engineering in United States Leader Award
  • 2022 - Research.com Materials Science in United States Leader Award
  • 2020 - IEEE Medal of Honor For a distinguished career of developing and putting into practice semiconductor models, particularly 3-D device structures, that have helped keep Moore's Law going over many decades.
  • 2015 - Fellow, National Academy of Inventors
  • 2012 - Fellow, The World Academy of Sciences
  • 2011 - Semiconductor Industry Association University Researcher Award
  • 2009 - IEEE Jun-ichi Nishizawa Medal "For technical contributions to MOS device reliability, scaling of CMOS and compact device modeling."
  • 2002 - IEEE Donald O. Pederson Award in Solid-State Circuits "For contributions to MOSFET physics and development of the BSIM model for CMOS circuit simulation."
  • 1998 - Monie A. Ferst Award, Sigma Xi
  • 1997 - Member of the National Academy of Engineering For contributions to the modeling integration-circuit devices and to the reliability and performance of VLSI systems.
  • 1990 - IEEE Fellow For contributions to the understanding of hot-electron effects in MOS devices.

Overview

Chenming Hu is affiliated with the University of California, Berkeley in the United States. Their research primarily focuses on the field of engineering, with a specialization in electrical and electronic engineering.

The scientist has contributed to several main topics in semiconductor research, which include:

  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Integrated Circuits and Semiconductor Failure Analysis
  • 3D IC and TSV technologies
  • Thin-Film Transistor Technologies

Chenming Hu's publications are concentrated in venues such as the Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials. The scientist's recently documented paper is titled "Effect of Dielectric Layer Scheme for High-Quality Silicon Channel in Monolithic 3DIC," published in 2020 within this venue.

The list of frequent co-authors collaborating with Chenming Hu includes:

  • Yogesh Singh Chauhan
  • Girish Pahwa
  • Avirup Dasgupta
  • Darsen D. Lu
  • Sriramkumar Venugopalan

Chenming Hu's awards and recognitions comprise several notable honors:

  • IEEE Medal of Honor (2020): For a distinguished career developing semiconductor models and 3-D device structures facilitating Moore's Law
  • Fellow, National Academy of Inventors (2015)
  • Fellow, The World Academy of Sciences (2012)
  • Semiconductor Industry Association University Researcher Award (2011)
  • IEEE Jun-ichi Nishizawa Medal (2009): For contributions to MOS device reliability, CMOS scaling, and device modeling
  • IEEE Donald O. Pederson Award in Solid-State Circuits (2002): For contributions to MOSFET physics and BSIM model development
  • Monie A. Ferst Award, Sigma Xi (1998)
  • Member of the National Academy of Engineering (1997): For contributions to modeling integrated-circuit devices and VLSI systems reliability
  • IEEE Fellow (1990): For understanding hot-electron effects in MOS devices

Best Publications

  • Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

    Chenming Hu;Simon C. Tam;Fu-Chieh Hsu;Ping-Keung Ko

  • FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

    D. Hisamoto;Wen-Chin Lee;J. Kedzierski;H. Takeuchi

  • MoS2 transistors with 1-nanometer gate lengths

    Sujay B. Desai;Sujay B. Desai;Surabhi R. Madhvapathy;Surabhi R. Madhvapathy;Angada B. Sachid;Angada B. Sachid;Juan Pablo Llinas;Juan Pablo Llinas

  • Electrical Breakdown in Thin Gate and Tunneling Oxides

    Ih-Chin Chen;S.E. Holland;Chenming Hu

  • A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors

    K.K. Hung;P.K. Ko;C. Hu;Y.C. Cheng

  • FinFET scaling to 10 nm gate length

    Bin Yu;Leland Chang;S. Ahmed;Haihong Wang

  • Sub 50-nm FinFET: PMOS

    Xuejue Huang;Wen-Chin Lee;Charles Kuo;D. Hisamoto

  • Enhanced ferroelectricity in ultrathin films grown directly on silicon.

    Suraj S. Cheema;Daewoong Kwon;Daewoong Kwon;Nirmaan Shanker;Roberto dos Reis

  • Modern Semiconductor Devices for Integrated Circuits

    Chenming Hu

  • Field-Effect Transistors Built from All Two-Dimensional Material Components

    Tania Roy;Mahmut Tosun;Mahmut Tosun;Jeong Seuk Kang;Jeong Seuk Kang;Angada B. Sachid

  • New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

    Y. Cao;T. Sato;M. Orshansky;D. Sylvester

  • Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation

    K.F. Schuegraf;Chenming Hu

  • Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

    Chenming Hu;Tsu-Jae King;Vivek Subramanian;Leland Chang

  • MOS capacitance measurements for high-leakage thin dielectrics

    K.J. Yang;Chenming Hu

  • Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

    F. Assaderaghi;D. Sinitsky;S.A. Parke;J. Bokor

  • Sub-50 nm P-channel FinFET

    Xuejue Huang;Wen-Chin Lee;C. Kuo;D. Hisamoto

  • MOSFET Modeling & BSIM3 User's Guide

    Yuhua Cheng;Chenming Hu

  • Lucky-electron model of channel hot-electron injection in MOSFET'S

    Simon Tam;Ping-Keung Ko;Chenming Hu

  • Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

    Yee Chia Yeo;Tsu Jae King;Chen-Ming Hu

  • Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography

    Yee-Chia Yeo;Burn-Jeng Lin;Chenming Hu

Frequent Co-Authors

Tsu-Jae King
Tsu-Jae King University of California, Berkeley
Fu-Liang Yang
Fu-Liang Yang Academia Sinica
Ping-Keung Ko
Ping-Keung Ko Hong Kong University of Science and Technology
Sayeef Salahuddin
Sayeef Salahuddin University of California, Berkeley
Mansun Chan
Mansun Chan Hong Kong University of Science and Technology
Ali M. Niknejad
Ali M. Niknejad University of California, Berkeley
Yogesh Singh Chauhan
Yogesh Singh Chauhan Indian Institute of Technology Kanpur
Sourabh Khandelwal
Sourabh Khandelwal Macquarie University
Jeffrey Bokor
Jeffrey Bokor University of California, Berkeley
Nathan W. Cheung
Nathan W. Cheung University of California, Berkeley

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