World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
90
Citations
24410
World Ranking
302
National Ranking
145

Materials Science

D-Index
92
Citations
25112
World Ranking
1556
National Ranking
486

Research.com Recognitions

  • 2013 - Member of the National Academy of Engineering For contributions to CMOS transistor technologies for advanced logic products.
  • 2012 - IEEE Jun-ichi Nishizawa Medal “For sustained leadership in developing innovative transistor technologies for advanced logic products.”

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Optoelectronics

Robert S. Chau mainly investigates Optoelectronics, Layer, Transistor, Gate dielectric and Substrate. His Optoelectronics research includes elements of Metal gate, Gate oxide, Semiconductor device and Electronic engineering. His study looks at the relationship between Layer and topics such as Oxide, which overlap with Oxide thin-film transistor.

The concepts of his Transistor study are interwoven with issues in CMOS, Nanotechnology, Silicon and Communication channel. His biological study spans a wide range of topics, including Field-effect transistor and High-κ dielectric. His work deals with themes such as Barrier layer, Metal and Germanium, which intersect with Substrate.

His most cited work include:

  • Semiconductor transistor having a stressed channel (402 citations)
  • Nonplanar transistors with metal gate electrodes (390 citations)
  • Integrated nanoelectronics for the future (294 citations)

What are the main themes of his work throughout his whole career to date?

His primary areas of investigation include Optoelectronics, Layer, Transistor, Substrate and Gate oxide. His research in Optoelectronics intersects with topics in Metal gate, Electronic engineering, Gate dielectric and Electrical engineering. The study incorporates disciplines such as High-κ dielectric and Dielectric in addition to Gate dielectric.

His work in the fields of Semiconductor device, Trench and Epitaxy overlaps with other areas such as Fin. His Transistor research incorporates themes from Nanowire, Nanotechnology, Silicon, Communication channel and CMOS. His Substrate study combines topics from a wide range of disciplines, such as Barrier layer and Germanium.

He most often published in these fields:

  • Optoelectronics (74.25%)
  • Layer (41.30%)
  • Transistor (33.18%)

What were the highlights of his more recent work (between 2013-2020)?

  • Optoelectronics (74.25%)
  • Layer (41.30%)
  • Transistor (33.18%)

In recent papers he was focusing on the following fields of study:

Optoelectronics, Layer, Transistor, Substrate and Silicon are his primary areas of study. His study on Semiconductor is often connected to Stack as part of broader study in Optoelectronics. His research in Semiconductor tackles topics such as Integrated circuit which are related to areas like Substrate.

Robert S. Chau works mostly in the field of Layer, limiting it down to topics relating to Perpendicular and, in certain cases, Analytical chemistry. His work carried out in the field of Transistor brings together such families of science as Gallium nitride, Nanotechnology, Breakdown voltage, Trench and Crystal structure. His studies in Silicon integrate themes in fields like Barrier layer, CMOS, Buffer and Microelectromechanical systems.

Between 2013 and 2020, his most popular works were:

  • Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications (66 citations)
  • III-N material structure for gate-recessed transistors (35 citations)
  • Perpendicular spin transfer torque memory (sttm) device with enhanced stability and method to form same (29 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Transistor
  • Integrated circuit

Robert S. Chau mostly deals with Optoelectronics, Layer, Transistor, Electrical engineering and Stack. His Optoelectronics research includes themes of Oxide, Substrate and Resistive random-access memory. His Substrate research is multidisciplinary, incorporating elements of Semiconductor device, Aspect ratio, Second source and Silicon-germanium.

Robert S. Chau has included themes like Die and Memory cell in his Layer study. His Transistor research is multidisciplinary, relying on both Gallium nitride, Nanotechnology, Semiconductor, Etching and Thermal expansion. His Dielectric research is multidisciplinary, incorporating perspectives in Barrier layer, Gate dielectric, High-electron-mobility transistor and Gate oxide.

Best Publications

  • A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

    K. Mistry;C. Allen;C. Auth;B. Beattie

  • A logic nanotechnology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;S. Cea

  • High performance fully-depleted tri-gate CMOS transistors

    B.S. Doyle;S. Datta;M. Doczy;S. Hareland

  • Nonplanar transistors with metal gate electrodes

    Justin K. Brask;Brian S. Doyle;Mark L. Doczy;Robert S. Chau

  • Semiconductor transistor having a stressed channel

    Anand Murthy;Robert S. Chau;Tahir Ghani;Kaizad R. Mistry

  • Integrated nanoelectronics for the future

    Robert Chau;Brian Doyle;Suman Datta;Jack Kavalieros

  • Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

    G. Dewey;B. Chu-Kung;J. Boardman;J. M. Fastenau

  • Semiconductor device and integrated circuit structure

    Rachmady Willy;Pillarisetty Ravi;Le Van H;Kavalieros Jack T

  • Method of forming a nonplanar transistor with sidewall spacers

    Justin K. Brask;Brian S. Doyle;Jack Kavalieros;Mark Doczy

  • Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

    B. Doyle;B. Boyanov;S. Datta;M. Doczy

  • Block Contact Architectures for Nanoscale Channel Transistors

    Marko Radosavljevic;Amlan Majumdar;Brian S. Doyle;Jack Kavalieros

  • Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

    J. Kavalieros;B. Doyle;S. Datta;G. Dewey

  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

    Justin K. Brask;Jack Kavalieros;Mark L. Doczy;Uday Shah

  • Tri-gate transistor device with stress incorporation layer and method of fabrication

    Scott A. Hareland;Robert S. Chau;Brian S. Doyle;Suman Datta

  • MOS transistor structure and method of fabrication

    Anand Murthy;Robert S. Chau;Patrick Morrow

  • Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

    Scott A. Hareland;Robert S. Chau;Brian S. Doyle;Rafael Rios

  • A 50 nm depleted-substrate CMOS transistor (DST)

    R. Chau;J. Kavalieros;B. Doyle;A. Murthy

  • Method for making a semiconductor device having a high-k gate dielectric

    Mark L. Doczy;Gilbert Dewey;Suman Datta;Sangwoo Pae

  • CMOS devices with a single work function gate electrode and method of fabrication

    Brian S. Doyle;Been-Yih Jin;Jack T. Kavalieros;Suman Datta

  • Method of fabricating a MOS transistor having a composite gate electrode

    Chau Robert S;Fraser David B;Cadien Kenneth C;Raghavan Gopal

  • Metal surface treatments for uniformly growing dielectric layers

    Gilbert Dewey;Matthew V. Metz;Jack Kavalieros;Robert S. Chau

Frequent Co-Authors

Brian S. Doyle
Brian S. Doyle Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Justin K. Brask
Justin K. Brask Intel (United States)
Mark L. Doczy
Mark L. Doczy Intel (United States)
Uday Shah
Uday Shah Intel (United States)
Marko Radosavljevic
Marko Radosavljevic Intel (United States)
Anand S. Murthy
Anand S. Murthy Intel (United States)
Mantu K. Hudait
Mantu K. Hudait Virginia Tech
Prashant Majhi
Prashant Majhi Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)

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