World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
68
Citations
15442
World Ranking
1035
National Ranking
436

Materials Science

D-Index
68
Citations
14947
World Ranking
4923
National Ranking
1300

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Electrical engineering

His primary areas of investigation include Optoelectronics, Transistor, Layer, Semiconductor and Substrate. The various areas that Brian S. Doyle examines in his Optoelectronics study include Field-effect transistor, Electronic engineering, Electrical engineering and Gate oxide. While the research belongs to areas of Gate oxide, he spends his time largely on the problem of Gate dielectric, intersecting his research to questions surrounding Semiconductor device and High-κ dielectric.

His Transistor research includes themes of Substrate and Nanotechnology. His study in Layer is interdisciplinary in nature, drawing from both Wafer, Oxide and Dielectric. His biological study deals with issues like Thin film, which deal with fields such as Metal and Integrated circuit.

His most cited work include:

  • Tri-gate devices and methods of fabrication (557 citations)
  • High performance fully-depleted tri-gate CMOS transistors (420 citations)
  • Nonplanar transistors with metal gate electrodes (390 citations)

What are the main themes of his work throughout his whole career to date?

Brian S. Doyle mostly deals with Optoelectronics, Layer, Transistor, Electrical engineering and Substrate. Brian S. Doyle interconnects Electronic engineering, Gate dielectric, Semiconductor device and Gate oxide in the investigation of issues within Optoelectronics. His Layer study integrates concerns from other disciplines, such as Oxide and Perpendicular.

His Transistor research integrates issues from CMOS, Nanotechnology and Integrated circuit. His study in the field of Capacitor, MOSFET, Voltage and Threshold voltage also crosses realms of Fin. His Substrate study incorporates themes from Trench, Silicon and Dielectric.

He most often published in these fields:

  • Optoelectronics (74.57%)
  • Layer (40.59%)
  • Transistor (32.76%)

What were the highlights of his more recent work (between 2017-2020)?

  • Optoelectronics (74.57%)
  • Layer (40.59%)
  • Transistor (32.76%)

In recent papers he was focusing on the following fields of study:

Optoelectronics, Layer, Transistor, Integrated circuit and Oxide are his primary areas of study. The Optoelectronics study combines topics in areas such as Electrical conductor, Tunnel magnetoresistance and Substrate. His research integrates issues of Spin-transfer torque, Perpendicular, Magnet and Voltage in his study of Layer.

His biological study spans a wide range of topics, including Terminal, Static random-access memory and Electronics. His Integrated circuit research is multidisciplinary, incorporating perspectives in Field-effect transistor, Thin film and Insulator. In his study, Logic gate, High speed memory, Gate oxide and Epitaxy is inextricably linked to Semiconductor, which falls within the broad field of Ferroelectricity.

Between 2017 and 2020, his most popular works were:

  • MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology (63 citations)
  • DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES (2 citations)
  • PROTECTION LAYERS FOR MAGNETIC TUNNEL JUNCTIONS (2 citations)

Best Publications

  • High performance fully-depleted tri-gate CMOS transistors

    B.S. Doyle;S. Datta;M. Doczy;S. Hareland

  • Nonplanar transistors with metal gate electrodes

    Justin K. Brask;Brian S. Doyle;Mark L. Doczy;Robert S. Chau

  • Integrated nanoelectronics for the future

    Robert Chau;Brian Doyle;Suman Datta;Jack Kavalieros

  • Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition

    Brian S. Doyle;Peng Cheng

  • Methodology for control of short channel effects in MOS transistors

    Brian S. Doyle;Brian Roberds

  • Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

    B. Doyle;B. Boyanov;S. Datta;M. Doczy

  • Block Contact Architectures for Nanoscale Channel Transistors

    Marko Radosavljevic;Amlan Majumdar;Brian S. Doyle;Jack Kavalieros

  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Self-aligned contacts for transistors

    Peter L. D. Chang;Brian S. Doyle

  • Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering

    Brian S. Doyle;Brian Roberds;Jin Lee

  • Tri-gate transistor device with stress incorporation layer and method of fabrication

    Scott A. Hareland;Robert S. Chau;Brian S. Doyle;Suman Datta

  • Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel

    Brian Roberds;Brian S. Doyle

  • A 50 nm depleted-substrate CMOS transistor (DST)

    R. Chau;J. Kavalieros;B. Doyle;A. Murthy

  • Method of increasing the mobility of MOS transistors by use of localized stress regions

    Brian S. Doyle;Brian Roberds;Jin Lee

  • CMOS devices with a single work function gate electrode and method of fabrication

    Brian S. Doyle;Been-Yih Jin;Jack T. Kavalieros;Suman Datta

  • Semiconductor transistor having a backfilled channel material

    Anand S. Murthy;Brian S. Doyle;Brian E. Roberds

  • SRAM and logic transistors with variable height multi-gate transistor architecture

    Suman Datta;Brian S. Doyle;Jack T. Kavalieros;Yih Wang

  • Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

    Robert Chau;Justin Brask;Suman Datta;Gilbert Dewey

  • Non-planar MOS structure with a strained channel region

    Brian S. Doyle;Suman Datta;Been-Yih Jin;Robert Chau

  • Method for Capacitively Coupling Electronic Devices

    Brian Doyle;Quat T. Vu;David B. Fraser

Frequent Co-Authors

Robert S. Chau
Robert S. Chau Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Mark L. Doczy
Mark L. Doczy Intel (United States)
Uday Shah
Uday Shah Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Anand S. Murthy
Anand S. Murthy Intel (United States)
Marko Radosavljevic
Marko Radosavljevic Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Prashant Majhi
Prashant Majhi Intel (United States)
Sasikanth Manipatruni
Sasikanth Manipatruni Intel (United States)

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