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Marko Radosavljevic

Marko Radosavljevic

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
57
Citations
15725
World Ranking
1935
National Ranking
760

Materials Science

D-Index
57
Citations
15575
World Ranking
7871
National Ranking
1952

Overview

Marko Radosavljevic is affiliated with Intel in the United States and has produced notable work within the fields of Engineering and Physics and Astronomy. Their research predominantly focuses on Electrical and Electronic Engineering as well as several specialized subfields including Condensed Matter Physics, Atomic and Molecular Physics and Optics, Materials Chemistry, and Electronic, Optical and Magnetic Materials.

The primary topics covered in Marko Radosavljevic's work include semiconductor materials and devices, GaN-based semiconductor devices and materials, advancements in semiconductor devices and circuit design, ferroelectric and negative capacitance devices, radio frequency integrated circuit design, silicon carbide semiconductor technologies, and ferroelectric and piezoelectric materials.

Frequent publication venues for their research are:

  • IEEE Transactions on Electron Devices
  • 2021 IEEE International Electron Devices Meeting (IEDM)
  • IEEE Microwave and Wireless Technology Letters
  • 2022 International Electron Devices Meeting (IEDM)
  • Nature Communications

Marko Radosavljevic has co-authored multiple papers with several researchers, notably including:

  • Han Wui Then
  • Pratik Koirala
  • Michael Beumer
  • Scott B. Clendenning
  • P. Fischer

Selected recent papers include:

  • "Process integration and future outlook of 2D transistors," 2023, Nature Communications
  • "Toward attojoule switching energy in logic transistors," 2022, Science
  • "Gallium Nitride and Silicon Transistors on 300 mm Silicon Wafers Enabled by 3-D Monolithic Heterogeneous Integration," 2020, IEEE Transactions on Electron Devices
  • "Advanced Scaling of Enhancement Mode High-K Gallium Nitride-on-300mm-Si(111) Transistor and 3D Layer Transfer GaN-Silicon Finfet CMOS Integration," 2021, 2021 IEEE International Electron Devices Meeting (IEDM)
  • "Enhancement-Mode 300-mm GaN-on-Si(111) With Integrated Si CMOS for Future mm-Wave RF Applications," 2023, IEEE Microwave and Wireless Technology Letters

Best Publications

  • Carbon nanotube composites for thermal management

    M. J Biercuk;Mark C Llaguno;M. Radosavljevic;J. K Hyun

  • Carbon nanotube composites for thermal management

    M.J. Biercuk;M.C. Llaguno;M. Radosavljevic;J.K. Hyun

  • Benchmarking nanotechnology for high-performance and low-power logic transistor applications

    R. Chau;S. Datta;M. Doczy;B. Doyle

  • Nonvolatile Molecular Memory Elements Based on Ambipolar Nanotube Field Effect Transistors

    M. Radosavljević;M. Freitag;K. V. Thadani;A. T. Johnson

  • Non-volatile molecular memory elements based on ambipolar nanotube field effect transistors

    M. Radosavljevic;M. Freitag;K. V. Thadani;A. T. Johnson

  • Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

    G. Dewey;B. Chu-Kung;J. Boardman;J. M. Fastenau

  • Tunneling versus thermionic emission in one-dimensional semiconductors.

    J. Appenzeller;M. Radosavljević;J. Knoch;Ph. Avouris

  • Block Contact Architectures for Nanoscale Channel Transistors

    Marko Radosavljevic;Amlan Majumdar;Brian S. Doyle;Jack Kavalieros

  • Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

    J. Kavalieros;B. Doyle;S. Datta;G. Dewey

  • Drain voltage scaling in carbon nanotube transistors

    M. Radosavljević;S. Heinze;J. Tersoff;Ph. Avouris

  • Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

    M. Radosavljevic;B. Chu-Kung;S. Corcoran;G. Dewey

  • IEEE International Electron Devices Meeting

    M. Radosavljevic;T. Ashley;A. Andreev;S. D. Coomber

  • Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

    Robert Chau;Justin Brask;Suman Datta;Gilbert Dewey

  • Unexpected scaling of the performance of carbon nanotube Schottky-barrier transistors

    S. Heinze;M. Radosavljević;J. Tersoff;Ph. Avouris

  • Controlled creation of a carbon nanotube diode by a scanned gate

    Marcus Freitag;Marko Radosavljevic;Yangxin Zhou;A. T. Johnson

  • Catalyst-Free Growth of Ordered Single-Walled Carbon Nanotube Networks

    V. Derycke;R. Martel;M. Radosavljević;and F. M. Ross

  • High performance of potassium n-doped carbon nanotube field-effect transistors

    M. Radosavljević;J. Appenzeller;Ph. Avouris;J. Knoch

  • Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

    M. Radosavljevic;G. Dewey;D. Basu;J. Boardman

  • CMOS implementation of Germanium, III-V nano-wires and nano-belts in grid-wound framework

    M Radosavljevic;R Pillarisetty;G Dewey;N Mukherjee

  • High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

    R. Pillarisetty;B. Chu-Kung;S. Corcoran;G. Dewey

  • High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

    M. Radosavljevic;T. Ashley;A. Andreev;S.D. Coomber

Frequent Co-Authors

Robert S. Chau
Robert S. Chau Intel (United States)
jack t kavalieros
jack t kavalieros Intel (United States)
matthew v metz
matthew v metz Intel (United States)
Mantu K. Hudait
Mantu K. Hudait Virginia Tech
Suman Datta
Suman Datta Georgia Institute of Technology
Brian S. Doyle
Brian S. Doyle Intel (United States)
Uday Shah
Uday Shah Intel (United States)
Phaedon Avouris
Phaedon Avouris IBM (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Joerg Appenzeller
Joerg Appenzeller Purdue University West Lafayette

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