World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
48
Citations
9246
World Ranking
3072
National Ranking
1155

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Silicon

Optoelectronics, Transistor, Silicon, Layer and Electronic engineering are his primary areas of study. His Optoelectronics research includes elements of Semiconductor device, Electrical engineering and Contact resistance. His Transistor research integrates issues from CMOS, Undercut, Semiconductor and Integrated circuit.

While the research belongs to areas of Silicon, Anand S. Murthy spends his time largely on the problem of Gate dielectric, intersecting his research to questions surrounding Metal gate, Gate oxide and Fin. His work on Epitaxy as part of general Layer study is frequently linked to Process, bridging the gap between disciplines. PMOS logic is closely connected to Oxide thin-film transistor in his research, which is encompassed under the umbrella topic of Electronic engineering.

His most cited work include:

  • Semiconductor transistor having a stressed channel (402 citations)
  • Contact resistance reduced p-mos transistors employing ge-rich contact layer (214 citations)
  • III-V layers for N-type and P-type MOS source-drain contacts (163 citations)

What are the main themes of his work throughout his whole career to date?

His main research concerns Optoelectronics, Transistor, Layer, Silicon and Epitaxy. His research on Optoelectronics often connects related topics like Substrate. His Transistor study is concerned with Electrical engineering in general.

His work on Gate oxide as part of general Electrical engineering study is frequently connected to Fabrication and Conductivity, therefore bridging the gap between diverse disciplines of science and establishing a new relationship between them. His study looks at the intersection of Silicon and topics like Electronic engineering with Oxide thin-film transistor. His work carried out in the field of Semiconductor brings together such families of science as Field-effect transistor and Dielectric.

He most often published in these fields:

  • Optoelectronics (87.64%)
  • Transistor (56.55%)
  • Layer (25.09%)

What were the highlights of his more recent work (between 2019-2021)?

  • Optoelectronics (87.64%)
  • Transistor (56.55%)
  • Epitaxy (17.60%)

In recent papers he was focusing on the following fields of study:

His primary areas of investigation include Optoelectronics, Transistor, Epitaxy, Integrated circuit and Silicon. His research integrates issues of Layer and Semiconductor device in his study of Optoelectronics. Anand S. Murthy has included themes like Etching, Doping and Germanium in his Transistor study.

His Germanium research is multidisciplinary, incorporating perspectives in Analytical chemistry and Silicon-germanium. His biological study spans a wide range of topics, including Electrical conductor and Semiconductor materials, Semiconductor. As part of one scientific family, Anand S. Murthy deals mainly with the area of Silicon, narrowing it down to issues related to the Arsenic, and often Second source.

Between 2019 and 2021, his most popular works were:

  • INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN REGIONS OF STACKED TRANSISTORS (3 citations)
  • GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING VERTICALLY DISCRETE SOURCE OR DRAIN STRUCTURES (2 citations)
  • STRAINED TUNABLE NANOWIRE STRUCTURES AND PROCESS (1 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Silicon
  • Transistor

Anand S. Murthy spends much of his time researching Optoelectronics, Transistor, Epitaxy, Integrated circuit and Dopant. Silicon and Nanowire are subfields of Optoelectronics in which his conducts study. His research integrates issues of Doping and Semiconductor in his study of Transistor.

His work deals with themes such as Semiconductor materials, Epitaxial material and Electrical conductor, which intersect with Doping. His Dopant study incorporates themes from Deposition, Thin-film transistor and Undercut. His work investigates the relationship between Semiconductor device and topics such as Buffer that intersect with problems in Substrate and Layer.

Best Publications

  • A 90-nm logic technology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;M. Alavi

  • High performance fully-depleted tri-gate CMOS transistors

    B.S. Doyle;S. Datta;M. Doczy;S. Hareland

  • Semiconductor transistor having a stressed channel

    Anand Murthy;Robert S. Chau;Tahir Ghani;Kaizad R. Mistry

  • Contact resistance reduced p-mos transistors employing ge-rich contact layer

    Glenn A. Glass;Anand S. Murthy

  • MOS transistor structure and method of fabrication

    Anand Murthy;Robert S. Chau;Patrick Morrow

  • A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

    S. Natarajan;M. Armstrong;M. Bost;R. Brain

  • A 50 nm depleted-substrate CMOS transistor (DST)

    R. Chau;J. Kavalieros;B. Doyle;A. Murthy

  • Semiconductor device having doped epitaxial region and its methods of fabrication

    Anand S. Murthy;Daniel Bourne Aubertine;Tahir Ghani;Abhijit Jayant Pethe

  • Semiconductor transistor having a backfilled channel material

    Anand S. Murthy;Brian S. Doyle;Brian E. Roberds

  • Method for fabricating a bipolar transistor base

    Ravindra Soman;Anand Murthy

  • III-V SEMICONDUCTOR DEVICE HAVING III-V SEMICONDUCTOR MATERIAL LAYER

    Glass Glenn A;Murthy Anand S;Ghani Tahir

  • Semiconductor device having deposited silicon regions and a method of fabrication

    Anand Murthy;Chia-Hong Jan;Ebrahim Andideh;Kevin Weldon

  • multi-gate transistor

    カペラーニ、アナリサ;Cappellani Annalisa;ガーニ、タヒア;Ghani Tahir

  • Graded high germanium compound films for strained semiconductor devices

    Danielle Simonelli;Anand Murthy

  • CMOS transistor junction regions formed by a CVD etching and deposition sequence

    Anand Murthy;Glenn A. Glass;Andrew N. Westmeyer;Michael L. Hattendorf

  • Transistor with improved tip profile and method of manufacture thereof

    Mark T. Bohr;Steven J. Keating;Thomas A. Letson;Anand S. Murthy

  • Nanowire transistor devices and forming techniques

    Glenn A. Glass;Kelin J. Kuhn;Seiyon Kim;Anand S. Murthy

  • Integration methods to fabricate internal spacers for nanowire devices

    Seiyon Kim;Kelin J. Kuhn;Tahir Ghani;Anand S. Murthy

  • 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

    R. Chau;J. Kavalieros;B. Roberds;R. Schenker

  • Method for forming an integrated circuit

    Anand S. Murthy;Glenn A. Glass;Andrew N. Westmeyer;Michael L. Hattendorf

  • TRANSISTORS WITH HIGH CONCENTRATION OF GERMANIUM

    Murthy Anand S;Glass Glenn A;Ghani Tahir;Pillarisetty Ravi

Frequent Co-Authors

Tahir Ghani
Tahir Ghani Intel (United States)
Robert S. Chau
Robert S. Chau Intel (United States)
Brian S. Doyle
Brian S. Doyle Intel (United States)
Mark T. Bohr
Mark T. Bohr Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Mark L. Doczy
Mark L. Doczy Intel (United States)
Prashant Majhi
Prashant Majhi Intel (United States)
Marko Radosavljevic
Marko Radosavljevic Intel (United States)

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