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Electronics and Electrical Engineering

D-Index
44
Citations
7578
World Ranking
3748
National Ranking
35

Overview

Yogesh Singh Chauhan is a researcher affiliated with the Indian Institute of Technology Kanpur in India. The body of work spans multiple fields within engineering and materials science, particularly focusing on semiconductor devices and materials.

Their main fields of study include:

  • Engineering
  • Materials Science

Within these broader fields, the research delves into several subfields such as:

  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics
  • Biomedical Engineering
  • Atomic and Molecular Physics, and Optics

The topics of their work cover a range of areas primarily related to semiconductor technology and device engineering. Key topics include:

  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Ferroelectric and Negative Capacitance Devices
  • GaN-based semiconductor devices and materials
  • Advanced Memory and Neural Computing
  • Radio Frequency Integrated Circuit Design
  • 2D Materials and Applications

Chauhan's recent papers highlight specific contributions to semiconductor research and device modeling:

  • First demonstration of in-memory computing crossbar using multi-level Cell FeFET (2023), Nature Communications
  • BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs (2020), IEEE Transactions on Electron Devices
  • Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology (2020), IEEE Transactions on Circuits and Systems I Regular Papers
  • Crossing the Nernst Limit (59 mV/pH) of Sensitivity Through Tunneling Transistor-Based Biosensor (2020), IEEE Sensors Journal
  • Two-Dimensional MoSi2N4: An Excellent 2-D Semiconductor for Field-Effect Transistors (2021), IEEE Transactions on Electron Devices

The publication record includes a substantial number of appearances in key academic venues, with frequent publications in:

  • IEEE Transactions on Electron Devices
  • IEEE Journal of the Electron Devices Society
  • arXiv (Cornell University)
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • SSRN Electronic Journal

Chauhan collaborates with various co-authors, among whom the most frequent are:

  • Hussam Amrouch
  • Ahtisham Pampori
  • Girish Pahwa
  • Chenming Hu
  • Somnath Bhowmick

Best Publications

  • FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard

    Yogesh Singh Chauhan;Darsen Duane Lu;Vanugopalan Sriramkumar;Sourabh Khandelwal

  • Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices

    S. Khandelwal;Y. S. Chauhan;T. A. Fjeldly

  • Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

    Girish Pahwa;Tapas Dutta;Amit Agarwal;Sourabh Khandelwal

  • FinFET modeling for IC simulation and design

    Chenming Hu;Darsen D Lu;Yogesh Singh Chauhan

  • Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior

    Girish Pahwa;Amit Agarwal;Yogesh Singh Chauhan

  • BSIM6: Analog and RF Compact Model for Bulk MOSFET

    Yogesh Singh Chauhan;Sriramkumar Venugopalan;Maria-Anna Chalkiadaki;Muhammed Ahosan Ul Karim

  • Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design

    Sourabh Khandelwal;Chandan Yadav;Shantanu Agnihotri;Yogesh Singh Chauhan

  • BSIM—SPICE Models Enable FinFET and UTB IC Designs

    Navid Paydavosi;Sriramkumar Venugopalan;Yogesh Singh Chauhan;Juan Pablo Duarte

  • ASM GaN: Industry Standard Model for GaN RF and Power Devices—Part 1: DC, CV, and RF Model

    Sourabh Khandelwal;Yogesh Singh Chauhan;Tor A. Fjeldly;Sudip Ghosh

  • Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

    Girish Pahwa;Tapas Dutta;Amit Agarwal;Yogesh Singh Chauhan

  • BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

    S. Khandelwal;Y. S. Chauhan;D. D. Lu;S. Venugopalan

  • Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

    Girish Pahwa;Tapas Dutta;Amit Agarwal;Yogesh Singh Chauhan

  • Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

    K. Akarvardar;C. Eggimann;D. Tsamados;Y. Singh Chauhan

  • Capacitance Modeling in Dual Field-Plate Power GaN HEMT for Accurate Switching Behavior

    Sheikh Aamir Ahsan;Sudip Ghosh;Khushboo Sharma;Avirup Dasgupta

  • ASM GaN: Industry Standard Model for GaN RF and Power Devices—Part-II: Modeling of Charge Trapping

    Sayed Ali Albahrani;Dhawal Mahajan;Jason Hodges;Yogesh Singh Chauhan

  • Thickness and electric-field-dependent polarizability and dielectric constant in phosphorene

    Piyush Kumar;B. S. Bhadoria;Sanjay Kumar;Somnath Bhowmick

  • BSIM-CMG: Standard FinFET compact model for advanced circuit design

    Juan Pablo Duarte;Sourabh Khandelwal;Aditya Medury;Chenming Hu

  • Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance

    Hussam Amrouch;Girish Pahwa;Amol D. Gaidhane;Jorg Henkel

  • Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

    Tapas Dutta;Girish Pahwa;Amit Ranjan Trivedi;Saurabh Sinha

  • RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications

    Shyam Parthasarathy;Amit Trivedi;Saurabh Sirohi;Robert Groves

  • Physics-Based Multi-Bias RF Large-Signal GaN HEMT Modeling and Parameter Extraction Flow

    Sheikh Aamir Ahsan;Sudip Ghosh;Sourabh Khandelwal;Yogesh Singh Chauhan

  • Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X I ON using compact modeling approach

    Girish Pahwa;Tapas Dutta;Amit Agarwal;Yogesh Singh Chauhan

Frequent Co-Authors

Chenming Hu
Chenming Hu University of California, Berkeley
Amit Agarwal
Amit Agarwal Indian Institute of Technology Kanpur
Adrian M. Ionescu
Adrian M. Ionescu École Polytechnique Fédérale de Lausanne
Ali M. Niknejad
Ali M. Niknejad University of California, Berkeley
Jorg Henkel
Jorg Henkel Karlsruhe Institute of Technology
Sayeef Salahuddin
Sayeef Salahuddin University of California, Berkeley
Christian Enz
Christian Enz École Polytechnique Fédérale de Lausanne
Tor A. Fjeldly
Tor A. Fjeldly Norwegian University of Science and Technology
Souvik Mahapatra
Souvik Mahapatra Indian Institute of Technology Bombay
Bich-Yen Nguyen
Bich-Yen Nguyen Soitec (France)

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